From: Yu-Chien Peter Lin <peterlin@andestech.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: <acme@kernel.org>, <adrian.hunter@intel.com>,
<ajones@ventanamicro.com>, <alexander.shishkin@linux.intel.com>,
<andre.przywara@arm.com>, <anup@brainfault.org>,
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Subject: Re: [PATCH v4 02/13] irqchip/riscv-intc: Allow large non-standard interrupt number
Date: Tue, 12 Dec 2023 18:17:41 +0800 [thread overview]
Message-ID: <ZXgzRZK8uqgmY84L@APC323> (raw)
In-Reply-To: <871qbwsn9h.ffs@tglx>
Hi Thomas,
On Fri, Dec 08, 2023 at 04:54:34PM +0100, Thomas Gleixner wrote:
> On Wed, Nov 22 2023 at 20:12, Yu Chien Peter Lin wrote:
> > Currently, the implementation of the RISC-V INTC driver uses the
> > interrupt cause as hwirq and has a limitation of supporting a
>
> s/hwirq/hardware interrupt/
>
> Please spell things out. We are not on Xitter here.
>
> > maximum of 64 hwirqs. However, according to the privileged spec,
> > interrupt causes >= 16 are defined for platform use.
> >
> > This limitation prevents us from fully utilizing the available
>
> This limitation prevents to fully utilize the ...
Okay, will fix.
Thanks,
Peter Lin
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next prev parent reply other threads:[~2023-12-12 10:20 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20231122121235.827122-1-peterlin@andestech.com>
[not found] ` <20231122121235.827122-6-peterlin@andestech.com>
2023-11-22 16:36 ` [PATCH v4 05/13] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Geert Uytterhoeven
[not found] ` <20231122121235.827122-8-peterlin@andestech.com>
2023-11-22 21:16 ` [PATCH v4 07/13] RISC-V: Move T-Head PMU to CPU feature alternative framework Guo Ren
2023-11-23 14:45 ` Conor Dooley
[not found] ` <20231122121235.827122-5-peterlin@andestech.com>
2023-11-23 14:38 ` [PATCH v4 04/13] dt-bindings: riscv: Add Andes interrupt controller compatible string Conor Dooley
[not found] ` <CA+V-a8t+vgrwDe9OxqMNHdcVX+qq76DuskF0ETCri4VeP-FAbg@mail.gmail.com>
2023-11-29 6:43 ` Yu-Chien Peter Lin
[not found] ` <20231122121235.827122-10-peterlin@andestech.com>
2023-11-22 21:14 ` [PATCH v4 09/13] dt-bindings: riscv: Add T-Head PMU extension description Guo Ren
2023-11-29 8:48 ` Yu-Chien Peter Lin
[not found] ` <IA1PR20MB49537364BDF1ADE185CA8FE4BB82A@IA1PR20MB4953.namprd20.prod.outlook.com>
2023-11-30 9:21 ` Yu-Chien Peter Lin
[not found] ` <IA1PR20MB4953A05B9162AA2659DE78A5BB82A@IA1PR20MB4953.namprd20.prod.outlook.com>
2023-11-30 12:58 ` Conor Dooley
[not found] ` <IA1PR20MB495378652B09B37E92D8BB04BB82A@IA1PR20MB4953.namprd20.prod.outlook.com>
2023-12-01 0:40 ` Conor Dooley
[not found] ` <IA1PR20MB4953460FE5BF431DD32CD860BB81A@IA1PR20MB4953.namprd20.prod.outlook.com>
2023-12-06 3:14 ` Yu-Chien Peter Lin
2023-11-23 14:48 ` Conor Dooley
2023-11-29 8:47 ` Yu-Chien Peter Lin
2023-11-29 12:33 ` Conor Dooley
[not found] ` <20231122121235.827122-12-peterlin@andestech.com>
2023-11-22 21:12 ` [PATCH v4 11/13] riscv: dts: allwinner: Add T-Head PMU extension Guo Ren
2023-11-23 14:58 ` Conor Dooley
2023-11-29 9:34 ` Yu-Chien Peter Lin
[not found] ` <20231122121235.827122-3-peterlin@andestech.com>
[not found] ` <871qbwsn9h.ffs@tglx>
2023-12-12 10:17 ` Yu-Chien Peter Lin [this message]
[not found] ` <20231122121235.827122-4-peterlin@andestech.com>
[not found] ` <87y1e4r8db.ffs@tglx>
2023-12-12 10:28 ` [PATCH v4 03/13] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu-Chien Peter Lin
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