From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6B7FDC3DA6E for ; Fri, 5 Jan 2024 19:22:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=XFVJ6MICRggsi3fVPEQT5F+P3LQj4uOcA9Zp4NjtzjM=; b=i46X4GwTq8BmeF AxgmoKau/6L8vF2DT3fbw68sB6RhXZgq7/vYH/lbPR+O7mpDS4pxBYdAdngO6hPecmH2Cysjy/qqz XC7oUFwwKKUoenSeXlsnoJ+cZh7AiLvBapxT4GdLf/RMnwOjMc9iDmQtY2e2udZyBBEhlIyMGQCpC YSR5vXYDvI7Wa+CB1gCnY29xrUUnFKzLZaFEV08Sq6r2FPD864nQvhcK3TZEOwXJFcIDotfbACn2R wPcigYCRleH/H4QlQ4bfvLm3gCKvUyeietJY9WDfwE+dqikPNIyasoIcmWdtWXjvbZUcir3LzjtuR 4WD2i4M6JPsQhn32roFw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rLplT-0005Nl-1v; Fri, 05 Jan 2024 19:21:55 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rLplP-0005Lb-22 for linux-arm-kernel@lists.infradead.org; Fri, 05 Jan 2024 19:21:53 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id B183761B76; Fri, 5 Jan 2024 19:21:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9A6F9C433C7; Fri, 5 Jan 2024 19:21:47 +0000 (UTC) Date: Fri, 5 Jan 2024 19:21:45 +0000 From: Catalin Marinas To: Elad Nachman Cc: will@kernel.org, thunder.leizhen@huawei.com, bhe@redhat.com, akpm@linux-foundation.org, yajun.deng@linux.dev, chris.zjh@huawei.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH] arm64: mm: Fix SOCs with DDR starting above zero Message-ID: References: <20240103170002.1793197-1-enachman@marvell.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240103170002.1793197-1-enachman@marvell.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240105_112151_714183_18A2E416 X-CRM114-Status: GOOD ( 17.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jan 03, 2024 at 07:00:02PM +0200, Elad Nachman wrote: > From: Elad Nachman > > Some SOCs, like the Marvell AC5/X/IM, have a combination > of DDR starting at 0x2_0000_0000 coupled with DMA controllers > limited to 31 and 32 bit of addressing. > This requires to properly arrange ZONE_DMA and ZONE_DMA32 for > these SOCs, so swiotlb and coherent DMA allocation would work > properly. > Change initialization so device tree dma zone bits are taken as > function of offset from DRAM start, and when calculating the > maximal zone physical RAM address for physical DDR starting above > 32-bit, combine the physical address start plus the zone mask > passed as parameter. > This creates the proper zone splitting for these SOCs: > 0..2GB for ZONE_DMA > 2GB..4GB for ZONE_DMA32 > 4GB..8GB for ZONE_NORMAL Please see this discussion: https://lore.kernel.org/all/ZU0QEL9ByWNYVki1@arm.com/ and follow-up patches from Baruch, though I haven't reviewed them yet: https://lore.kernel.org/all/fae5b1180161a7d8cd626a96f5df80b0a0796b8b.1703683642.git.baruch@tkos.co.il/ The problem is that the core code pretty much assumes that DRAM starts from 0. No matter how you massage the zones in the arm64 kernel for your case, memblock_start_of_DRAM() + (2 << zone_dma_bits) won't be a power of two and therefore zone_dma_bits in the core code cannot describe what you need. I can see Baruch added a zone_dma_off assuming it's the same for all DMA-capable devices on that SoC (well, those with a coherent mask smaller than 64-bit). I need to think a bit more about this. Anyway, we first need to address the mask/bits comparisons in the core code, maybe changing bits to a physical limit instead and take the device DMA offset into account. After that we can look at how to correctly set up the DMA zones on arm64. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel