From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B4013C3DA6E for ; Mon, 8 Jan 2024 15:55:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=iVqrxuKgTVmf6Yr63//oYSGW3nkMAVHrEU15j+sn7uQ=; b=JSjsUXfVqO0tMV Nd2yfAI7blGHum1wtHERP6AEeryymG57vn+HVnZ4A/zvX++bzxjmvt2zNF8Y0ybAscaW4znwfg0b2 CVvXq+fflEVpp62wmUWPULiyyaKrHD4whn3gZhn2J0rMIMEhkfespMeGiBpTW1sWS23Hm5C8dm/0/ OxPWpQtI9AZPTOgcDcvpIDPvKFm9f1RXrsrWCNncfps3PS7K3kBojALkCY1MUnl78VkQc/fjNZkhd QtsC7/SMv9SkOUdjVE4ro06FRlY6g15qoAQbK6SyfbRl989iQsl9Y4dN3MUacUF3hcqwPA5L/SL7h WXoTtTdvLSlUW+i0kDoQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rMry1-005Z2P-14; Mon, 08 Jan 2024 15:55:09 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rMrxy-005Z26-0k for linux-arm-kernel@lists.infradead.org; Mon, 08 Jan 2024 15:55:07 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 087B6C15; Mon, 8 Jan 2024 07:55:48 -0800 (PST) Received: from FVFF77S0Q05N (unknown [10.57.89.149]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1DF453F64C; Mon, 8 Jan 2024 07:55:00 -0800 (PST) Date: Mon, 8 Jan 2024 15:54:58 +0000 From: Mark Rutland To: "Brandt, Oliver - Lenze" Cc: "linux-arm-kernel@lists.infradead.org" , "will@kernel.org" , "catalin.marinas@arm.com" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH] arm64: mm: disable PAN during caches_clean_inval_user_pou Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240108_075506_339383_CF23E359 X-CRM114-Status: GOOD ( 18.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Oliver, On Mon, Jan 08, 2024 at 01:00:39PM +0000, Brandt, Oliver - Lenze wrote: > Using the cacheflush() syscall from an 32-bit user-space fails when > ARM64_PAN is used. We 'll get an endless loop: > > 1. executing "dc cvau, x2" results in raising an abort > 2. abort handler does not fix the reason for the abort and > returns to 1. > > Disabling PAN for the time of the cache maintenance fixes this. Hmm... the ARM ARM says PSTATE.PAN is not supposed to affect DC CVAU. Looking at the latest ARM ARM (ARM DDI 0487J.a), R_PMTWB states: | The PSTATE.PAN bit has no effect on all of the following: | | o Instruction fetches. | o Data cache instructions, except DC ZVA. | o If FEAT_PAN2 is not implemented, then address translation instructions. | o If FEAT_PAN2 is implemented, then the address translation instructions | other than AT S1E1RP and AT S1E1WP. So IIUC, DC CVAU shouldn't be affected by PAN. This could be a CPU bug; which CPU are you seeing this with? Mark. > Fixes: 338d4f49d6f7 ("arm64: kernel: Add support for Privileged Access Never") > Cc: stable@vger.kernel.org > Signed-off-by: Oliver Brandt > --- > arch/arm64/mm/cache.S | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S > index 503567c864fde..333c4c2baa568 100644 > --- a/arch/arm64/mm/cache.S > +++ b/arch/arm64/mm/cache.S > @@ -70,10 +70,12 @@ SYM_FUNC_ALIAS(__pi_caches_clean_inval_pou, caches_clean_inval_pou) > */ > SYM_FUNC_START(caches_clean_inval_user_pou) > uaccess_ttbr0_enable x2, x3, x4 > + ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, CONFIG_ARM64_PAN) > > caches_clean_inval_pou_macro 2f > mov x0, xzr > 1: > + ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, CONFIG_ARM64_PAN) > uaccess_ttbr0_disable x1, x2 > ret > 2: > -- > 2.43.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel