From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B61B0C47258 for ; Wed, 17 Jan 2024 13:29:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=s+yj5nLztqjAI/B4ROMqDZMo4UoeiA+PWEAUlYwzAgo=; b=43XICPfVPCmR5L P50y9y5m4vQbQMnKQik5NNenZ770UBMmnQYJEH1j1Vu+qPpNzcdi0J6m6XCz7ps5QC932JSdDWLC6 9MWN6IIRhdNMC7e187kv6ln4c2vLMQiMuqR3GzCiDAsjk6E+DHDkVlbz3Qb/K+Ea9ZV8UZ7p84P2B dAu5SSFXkaJ05yQ373CQdtRZdqWex2uFHmUtVecwdMXz7NAMnmY4yFnUIrEl4MZfw/8KgD8czDog+ IWOMPdC9RVrEyDWI+Cs/tMdIfxKfWBqSLlQ1kCqq2p8/ifyqdJK5CTMY8EQ+YbZfxcRSrC8iym7MP 5ljc+sSINI7ZQwlI7Ifg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rQ5yu-00GW0i-0E; Wed, 17 Jan 2024 13:29:24 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rQ5yq-00GVvm-1x for linux-arm-kernel@lists.infradead.org; Wed, 17 Jan 2024 13:29:22 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C492B11FB; Wed, 17 Jan 2024 05:30:00 -0800 (PST) Received: from FVFF77S0Q05N.cambridge.arm.com (FVFF77S0Q05N.cambridge.arm.com [10.1.37.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BEC4F3F766; Wed, 17 Jan 2024 05:29:12 -0800 (PST) Date: Wed, 17 Jan 2024 13:29:06 +0000 From: Mark Rutland To: Jason Gunthorpe Cc: Catalin Marinas , Niklas Schnelle , Leon Romanovsky , Arnd Bergmann , linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rdma@vger.kernel.org, llvm@lists.linux.dev, Michael Guralnik , Nathan Chancellor , Nick Desaulniers , Will Deacon , Marc Zyngier Subject: Re: [PATCH rdma-next 1/2] arm64/io: add memcpy_toio_64 Message-ID: References: <20231204182330.GK1493156@nvidia.com> <20231205175127.GJ2692119@nvidia.com> <20231205195130.GM2692119@nvidia.com> <20231206125919.GP2692119@nvidia.com> <20240116185121.GB980613@nvidia.com> <20240117123618.GD734935@nvidia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240117123618.GD734935@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240117_052920_720530_618A98A0 X-CRM114-Status: GOOD ( 17.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jan 17, 2024 at 08:36:18AM -0400, Jason Gunthorpe wrote: > On Wed, Jan 17, 2024 at 12:30:00PM +0000, Mark Rutland wrote: > > On Tue, Jan 16, 2024 at 02:51:21PM -0400, Jason Gunthorpe wrote: > > > Hey Catalin, > > > > > > I'm just revising this and I'm wondering if you know why ARM64 has this: > > > > > > #define __raw_writeq __raw_writeq > > > static __always_inline void __raw_writeq(u64 val, volatile void __iomem *addr) > > > { > > > asm volatile("str %x0, [%1]" : : "rZ" (val), "r" (addr)); > > > } > > > > > > Instead of > > > > > > #define __raw_writeq __raw_writeq > > > static __always_inline void __raw_writeq(u64 val, volatile void __iomem *addr) > > > { > > > asm volatile("str %x0, %1" : : "rZ" (val), "m" (*(volatile u64 *)addr)); > > > } > > > > > > ?? Like x86 has. > > > > I believe this is for the same reason as doing so in all of our other IO > > accessors. > > > > We've deliberately ensured that our IO accessors use a single base register > > with no offset as this is the only form that HW can represent in ESR_ELx.ISS.SRT > > when reporting a stage-2 abort, which a hypervisor may use for > > emulating IO. > > Wow, harming bare metal performace to accommodate imperfect emulation > sounds like a horrible reason :( Having working functionality everywhere is a very good reason. :) > So what happens with this patch where IO is done with STP? Are you > going to tell me I can't do it because of this? I'm not personally going to make that judgement, but it's certainly something for Catalin and Will to consider (and I've added Marc in case he has any opinion). Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel