From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6ADA3C47258 for ; Wed, 17 Jan 2024 14:08:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=RId4wsTVBuB2+iyq3B01tkAjSA3bX6LnZ8Z8HnS9j2Q=; b=yoyg7u4fQHxveS yiLIy/RQeBMWZA7UDUa66zGjJnMVYdzymxkjTCpQMQmcngwPaj7FvzVrSFYmnuuplA7mxZEiyGO++ /F8vA5kK6sEZBXVScHuNk7W0v6PJ8eb2WBHe/F/BKDMBpMV5qo2oCeQ5Ai9iMd/gtpFSBbM7NUCvE Wcjssn0o7mxehOysDkhTIMQBJ4/rfHgCCAgG/EbxjbtJaZJ4HZyvOiOl28hezVHIlRMflM4NcWStC Uhmq0J5zS2B5EovxiTz32Qs/aoL9CLVJpn4Eia1gqQYKG3I8zSDMrerHAl+gZxACV/zYmkyHuAlN5 9x8rO+7+fr3fA+tMPoAA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rQ6Zo-00Gt2T-2c; Wed, 17 Jan 2024 14:07:32 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rQ6Zl-00Gszu-2d for linux-arm-kernel@lists.infradead.org; Wed, 17 Jan 2024 14:07:31 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9B01A11FB; Wed, 17 Jan 2024 06:08:12 -0800 (PST) Received: from FVFF77S0Q05N.cambridge.arm.com (FVFF77S0Q05N.cambridge.arm.com [10.1.37.172]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B76FB3F5A1; Wed, 17 Jan 2024 06:07:24 -0800 (PST) Date: Wed, 17 Jan 2024 14:07:16 +0000 From: Mark Rutland To: Jason Gunthorpe Cc: Catalin Marinas , Niklas Schnelle , Leon Romanovsky , Arnd Bergmann , linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rdma@vger.kernel.org, llvm@lists.linux.dev, Michael Guralnik , Nathan Chancellor , Nick Desaulniers , Will Deacon Subject: Re: [PATCH rdma-next 1/2] arm64/io: add memcpy_toio_64 Message-ID: References: <20231204182330.GK1493156@nvidia.com> <20231205175127.GJ2692119@nvidia.com> <20231205195130.GM2692119@nvidia.com> <20231206125919.GP2692119@nvidia.com> <20240116185121.GB980613@nvidia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240117_060729_908360_25B16D7F X-CRM114-Status: GOOD ( 14.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jan 17, 2024 at 12:30:00PM +0000, Mark Rutland wrote: > On Tue, Jan 16, 2024 at 02:51:21PM -0400, Jason Gunthorpe wrote: > > Hey Catalin, > > > > I'm just revising this and I'm wondering if you know why ARM64 has this: > > > > #define __raw_writeq __raw_writeq > > static __always_inline void __raw_writeq(u64 val, volatile void __iomem *addr) > > { > > asm volatile("str %x0, [%1]" : : "rZ" (val), "r" (addr)); > > } > > > > Instead of > > > > #define __raw_writeq __raw_writeq > > static __always_inline void __raw_writeq(u64 val, volatile void __iomem *addr) > > { > > asm volatile("str %x0, %1" : : "rZ" (val), "m" (*(volatile u64 *)addr)); > > } > > > > ?? Like x86 has. > > I believe this is for the same reason as doing so in all of our other IO > accessors. > > We've deliberately ensured that our IO accessors use a single base register > with no offset as this is the only form that HW can represent in ESR_ELx.ISS.SRT > when reporting a stage-2 abort, which a hypervisor may use for emulating IO. FWIW, IIUC the immediate-offset forms *without* writeback can still be reported usefully in ESR_ELx, so I believe that we could use the "o" constraint for the __raw_write*() functions, e.g. static __always_inline void __raw_writeq(u64 val, volatile void __iomem *addr) { asm volatile("str %x0, %1" : : "rZ" (val), "o" (*(volatile u64 *)addr)); } However, the __raw_read*() functions would still need to use "r" due to ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE. Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel