From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 803C0C47E49 for ; Wed, 24 Jan 2024 12:46:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=WCr5lmdBme8UltrQxFnCFsvnIMAltVZPFGZlB47FttI=; b=XW6/NNb+D+LhOU If6CGkw5fBCFCzAM3YKNw9NmDQUS/hibdW2N46wHMV2+IXRAADm4v7zxvYxAN0t1GgkWAE+NFqEOc PuN+ssAR2NDdOLKA/MQdObPKl3Xp+11n6eVxCXXiIYuWnPxN2tCXKY4YtfoOaXbqn7q8rQoJr68jp l9NngkP9Wir9fJggvmUhnA99wmI+AK6t7wYPab809RNywcmA+d5Q5+uYnEGwzAVLqLRTyg/hVUmMi fCyLH5yL5na4IIctZD3HYKqhbSOp7futxnuKuj1+lQc0LQxxqcib1hv7YYQgYyEGUVvPvwU567UH6 e62hYlvUif/ZWemAqQPA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1rScdR-003Ipm-2A; Wed, 24 Jan 2024 12:45:41 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1rSbUJ-002mnu-0P for linux-arm-kernel@bombadil.infradead.org; Wed, 24 Jan 2024 11:32:11 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=9RWctULCgwtceQRjZ5eeSqnYnDwIiDBq+5zJAafwKCk=; b=Dkdxvao7iVpy16ogPbp56wjPPu P5gPVIF8SDMMPuv8obCQBQ4UQ+l1SzCfvs65Gmyr2pCb8k63IJjwtl3pBqwNat15GL1mafCh34ng6 Kw3i4dzmqun1dwglKUJBQEglDzSlzt2NJpC3H48t7YTRt7xRvoutCSWXK3gnOKjQjU3rroChCDLAx Mi5jiGYjRVixmeLzoTlgfgxOGYn9MGK36kBI2v57JC9HrBYMAqQVUxhEAJKOu/y7v40OcHOGjdg6o ldVkgCfslahY7xuCszqx3qZ7HIcUc6FAu+ajqZ7R20mlZwf0ui6+X22hajnKnXxIbgXUPeVRTZoUe zoEtWgoQ==; Received: from foss.arm.com ([217.140.110.172]) by desiato.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rSbUF-00000004QxY-0n8W for linux-arm-kernel@lists.infradead.org; Wed, 24 Jan 2024 11:32:09 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 152841FB; Wed, 24 Jan 2024 03:32:49 -0800 (PST) Received: from FVFF77S0Q05N.cambridge.arm.com (FVFF77S0Q05N.cambridge.arm.com [10.1.30.162]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5BF243F762; Wed, 24 Jan 2024 03:32:02 -0800 (PST) Date: Wed, 24 Jan 2024 11:31:57 +0000 From: Mark Rutland To: Jason Gunthorpe Cc: Will Deacon , Catalin Marinas , Niklas Schnelle , Leon Romanovsky , Arnd Bergmann , linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rdma@vger.kernel.org, llvm@lists.linux.dev, Michael Guralnik , Nathan Chancellor , Nick Desaulniers Subject: Re: [PATCH rdma-next 1/2] arm64/io: add memcpy_toio_64 Message-ID: References: <20231205195130.GM2692119@nvidia.com> <20231206125919.GP2692119@nvidia.com> <20240116185121.GB980613@nvidia.com> <20240117152822.GI734935@nvidia.com> <20240117160528.GA3398@willie-the-truck> <20240118161843.GN734935@nvidia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240118161843.GN734935@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240124_113207_671346_32B93C20 X-CRM114-Status: GOOD ( 23.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jan 18, 2024 at 12:18:43PM -0400, Jason Gunthorpe wrote: > On Wed, Jan 17, 2024 at 04:05:29PM +0000, Will Deacon wrote: > > On Wed, Jan 17, 2024 at 11:28:22AM -0400, Jason Gunthorpe wrote: > > > On Wed, Jan 17, 2024 at 02:07:16PM +0000, Mark Rutland wrote: > > > > > > > > I believe this is for the same reason as doing so in all of our other IO > > > > > accessors. > > > > > > > > > > We've deliberately ensured that our IO accessors use a single base register > > > > > with no offset as this is the only form that HW can represent in ESR_ELx.ISS.SRT > > > > > when reporting a stage-2 abort, which a hypervisor may use for emulating IO. > > > > > > > > FWIW, IIUC the immediate-offset forms *without* writeback can still be reported > > > > usefully in ESR_ELx, so I believe that we could use the "o" constraint for the > > > > __raw_write*() functions, e.g. > > > > > > > > static __always_inline void __raw_writeq(u64 val, volatile void __iomem *addr) > > > > { > > > > asm volatile("str %x0, %1" : : "rZ" (val), "o" (*(volatile u64 *)addr)); > > > > } > > > > > > "o" works well in the same simple memcpy loop: > > > > > > add x2, x1, w2, uxtw 3 > > > cmp x1, x2 > > > bcs .L1 > > > .L3: > > > ldp x10, x9, [x1] > > > ldp x8, x7, [x1, 16] > > > ldp x6, x5, [x1, 32] > > > ldp x4, x3, [x1, 48] > > > str x10, [x0] > > > str x9, [x0, 8] > > > str x8, [x0, 16] > > > str x7, [x0, 24] > > > str x6, [x0, 32] > > > str x5, [x0, 40] > > > str x4, [x0, 48] > > > str x3, [x0, 56] > > > add x1, x1, 64 > > > add x0, x0, 64 > > > cmp x2, x1 > > > bhi .L3 > > > .L1: > > > ret > > > > > > Seems intersting to pursue? > > > > I've seen the compiler struggle with plain "o" in the past ("Impossible > > constraint in asm") so we might want "Qo" if we go down this route. > > I'll stick a patch in 0-day and lets see if there are explosions. "Qo" > generates the same assembly. > > So to summarize: > - We don't like "m" because something about virtualization > traps breaks with post/pre indexed forms like: > str x1, [x0, 8]! > And "m" will allow the compiler to emit that. > - o selects only base register plus offset so it is OK > - Q allows base register only (no offset) on some compilers that > won't allow o for 0 offset > - read side stays at 'r' due to an alternates errata workaround > requiring ldar which doesn't accept the same effective address > as ldr. FWIW I've sent a patch out with a commit message describing all of the above (with you, Catalin, Marc, and Will Cc'd). It hasn't appeared on lore yet, but it should eventually show up at: https://lore.kernel.org/linux-arm-kernel/20240124111259.874975-1-mark.rutland@arm.com/ Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel