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[34.140.83.185]) by smtp.gmail.com with ESMTPSA id p12-20020a05600c358c00b0040fafc8bb3asm1829317wmq.9.2024.01.31.06.50.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jan 2024 06:50:46 -0800 (PST) Date: Wed, 31 Jan 2024 14:50:42 +0000 From: Mostafa Saleh To: Jason Gunthorpe Cc: iommu@lists.linux.dev, Joerg Roedel , linux-arm-kernel@lists.infradead.org, Robin Murphy , Will Deacon , Moritz Fischer , Moritz Fischer , Michael Shavit , Nicolin Chen , patches@lists.linux.dev, Shameer Kolothum Subject: Re: [PATCH v4 04/16] iommu/arm-smmu-v3: Move the STE generation for S1 and S2 domains into functions Message-ID: References: <0-v4-c93b774edcc4+42d2b-smmuv3_newapi_p1_jgg@nvidia.com> <4-v4-c93b774edcc4+42d2b-smmuv3_newapi_p1_jgg@nvidia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <4-v4-c93b774edcc4+42d2b-smmuv3_newapi_p1_jgg@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240131_065050_338362_34A7AEEE X-CRM114-Status: GOOD ( 23.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Jason, On Thu, Jan 25, 2024 at 07:57:14PM -0400, Jason Gunthorpe wrote: > This is preparation to move the STE calculation higher up in to the call > chain and remove arm_smmu_write_strtab_ent(). These new functions will be > called directly from attach_dev. > > Reviewed-by: Moritz Fischer > Reviewed-by: Michael Shavit > Reviewed-by: Nicolin Chen > Tested-by: Shameer Kolothum > Tested-by: Nicolin Chen > Tested-by: Moritz Fischer > Signed-off-by: Jason Gunthorpe > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 115 +++++++++++--------- > 1 file changed, 62 insertions(+), 53 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index df8fc7b87a7907..910156881423e0 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -1516,13 +1516,68 @@ static void arm_smmu_make_bypass_ste(struct arm_smmu_ste *target) > FIELD_PREP(STRTAB_STE_1_SHCFG, STRTAB_STE_1_SHCFG_INCOMING)); > } > > +static void arm_smmu_make_cdtable_ste(struct arm_smmu_ste *target, > + struct arm_smmu_master *master, > + struct arm_smmu_ctx_desc_cfg *cd_table) master already include cd_table in "master->cd_table", why do we need to pass it separately? > +{ > + struct arm_smmu_device *smmu = master->smmu; > + > + memset(target, 0, sizeof(*target)); > + target->data[0] = cpu_to_le64( > + STRTAB_STE_0_V | > + FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS) | > + FIELD_PREP(STRTAB_STE_0_S1FMT, cd_table->s1fmt) | > + (cd_table->cdtab_dma & STRTAB_STE_0_S1CTXPTR_MASK) | > + FIELD_PREP(STRTAB_STE_0_S1CDMAX, cd_table->s1cdmax)); > + > + target->data[1] = cpu_to_le64( > + FIELD_PREP(STRTAB_STE_1_S1DSS, STRTAB_STE_1_S1DSS_SSID0) | > + FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) | > + FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) | > + FIELD_PREP(STRTAB_STE_1_S1CSH, ARM_SMMU_SH_ISH) | > + ((smmu->features & ARM_SMMU_FEAT_STALLS && > + !master->stall_enabled) ? > + STRTAB_STE_1_S1STALLD : > + 0) | > + FIELD_PREP(STRTAB_STE_1_EATS, > + master->ats_enabled ? STRTAB_STE_1_EATS_TRANS : 0) | > + FIELD_PREP(STRTAB_STE_1_STRW, > + (smmu->features & ARM_SMMU_FEAT_E2H) ? > + STRTAB_STE_1_STRW_EL2 : > + STRTAB_STE_1_STRW_NSEL1)); > +} > + > +static void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, > + struct arm_smmu_master *master, > + struct arm_smmu_domain *smmu_domain) Similary, master already has the domain in "master->domain". > +{ > + struct arm_smmu_s2_cfg *s2_cfg = &smmu_domain->s2_cfg; > + > + memset(target, 0, sizeof(*target)); > + target->data[0] = cpu_to_le64( > + STRTAB_STE_0_V | > + FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS)); > + > + target->data[1] = cpu_to_le64( > + FIELD_PREP(STRTAB_STE_1_EATS, > + master->ats_enabled ? STRTAB_STE_1_EATS_TRANS : 0)); > + > + target->data[2] = cpu_to_le64( > + FIELD_PREP(STRTAB_STE_2_S2VMID, s2_cfg->vmid) | > + FIELD_PREP(STRTAB_STE_2_VTCR, s2_cfg->vtcr) | > + STRTAB_STE_2_S2AA64 | > +#ifdef __BIG_ENDIAN > + STRTAB_STE_2_S2ENDI | > +#endif > + STRTAB_STE_2_S2PTW | > + STRTAB_STE_2_S2R); > + > + target->data[3] = cpu_to_le64(s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK); > +} > + > static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, > struct arm_smmu_ste *dst) > { > - u64 val; > - struct arm_smmu_device *smmu = master->smmu; > - struct arm_smmu_ctx_desc_cfg *cd_table = NULL; > - struct arm_smmu_s2_cfg *s2_cfg = NULL; > struct arm_smmu_domain *smmu_domain = master->domain; > struct arm_smmu_ste target = {}; > > @@ -1537,61 +1592,15 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, > > switch (smmu_domain->stage) { > case ARM_SMMU_DOMAIN_S1: > - cd_table = &master->cd_table; > + arm_smmu_make_cdtable_ste(&target, master, &master->cd_table); > break; > case ARM_SMMU_DOMAIN_S2: > - s2_cfg = &smmu_domain->s2_cfg; > + arm_smmu_make_s2_domain_ste(&target, master, smmu_domain); > break; > case ARM_SMMU_DOMAIN_BYPASS: > arm_smmu_make_bypass_ste(&target); > - arm_smmu_write_ste(master, sid, dst, &target); > - return; > + break; > } > - > - /* Nuke the existing STE_0 value, as we're going to rewrite it */ > - val = STRTAB_STE_0_V; > - > - if (cd_table) { > - u64 strw = smmu->features & ARM_SMMU_FEAT_E2H ? > - STRTAB_STE_1_STRW_EL2 : STRTAB_STE_1_STRW_NSEL1; > - > - target.data[1] = cpu_to_le64( > - FIELD_PREP(STRTAB_STE_1_S1DSS, STRTAB_STE_1_S1DSS_SSID0) | > - FIELD_PREP(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) | > - FIELD_PREP(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) | > - FIELD_PREP(STRTAB_STE_1_S1CSH, ARM_SMMU_SH_ISH) | > - FIELD_PREP(STRTAB_STE_1_STRW, strw)); > - > - if (smmu->features & ARM_SMMU_FEAT_STALLS && > - !master->stall_enabled) > - target.data[1] |= cpu_to_le64(STRTAB_STE_1_S1STALLD); > - > - val |= (cd_table->cdtab_dma & STRTAB_STE_0_S1CTXPTR_MASK) | > - FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S1_TRANS) | > - FIELD_PREP(STRTAB_STE_0_S1CDMAX, cd_table->s1cdmax) | > - FIELD_PREP(STRTAB_STE_0_S1FMT, cd_table->s1fmt); > - } > - > - if (s2_cfg) { > - target.data[2] = cpu_to_le64( > - FIELD_PREP(STRTAB_STE_2_S2VMID, s2_cfg->vmid) | > - FIELD_PREP(STRTAB_STE_2_VTCR, s2_cfg->vtcr) | > -#ifdef __BIG_ENDIAN > - STRTAB_STE_2_S2ENDI | > -#endif > - STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2AA64 | > - STRTAB_STE_2_S2R); > - > - target.data[3] = cpu_to_le64(s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK); > - > - val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS); > - } > - > - if (master->ats_enabled) > - target.data[1] |= cpu_to_le64(FIELD_PREP(STRTAB_STE_1_EATS, > - STRTAB_STE_1_EATS_TRANS)); > - > - target.data[0] = cpu_to_le64(val); > arm_smmu_write_ste(master, sid, dst, &target); > } > > -- > 2.43.0 Reviewed-by: Mostafa Saleh Thanks, Mostafa _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel