From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0B1D8C48BC1 for ; Wed, 14 Feb 2024 18:15:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=mq7ZpIWRDXBxcJGVsNXgZDs9ZSnHOntiHEDpNtDHaNo=; b=EVuJnwdgUVrKXZ +Z9WupDTh9iex05ivohfCK0T0C0pJv9OUJIY5xmht6QAkojXwdCxMacvwNScIrUSiLAKREUMAgQbA RT6ITI0BjAJR0zhqm9akjSVEx+6Vb28RgjCX6LjRB2Vbgq51VJF7WswomTJK22/65GW6uiwTyZuDE cIDZAov6P+i9RS64i9iLyr24j2CjRx/yXTFCmeysMkuW+E2VftFky4b4kIPLVJkEnfZ1ULaTmJeRy pgSQg1X3ZGiHUUl1B3rRatTTdjFtJ6ky4WNqwIQdt+mxvuREbdkZS2p8/Z9Wi45Pp8Nm92XQq3y2o u23bHk31WEi2ov6B3TrQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1raJmm-0000000Dtvn-3nmC; Wed, 14 Feb 2024 18:15:08 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1raJmj-0000000Dtuh-3Yqj for linux-arm-kernel@lists.infradead.org; Wed, 14 Feb 2024 18:15:07 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 28EE21FB; Wed, 14 Feb 2024 10:15:43 -0800 (PST) Received: from FVFF77S0Q05N (unknown [10.57.64.145]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id ED1813F7B4; Wed, 14 Feb 2024 10:14:59 -0800 (PST) Date: Wed, 14 Feb 2024 18:14:51 +0000 From: Mark Rutland To: Easwar Hariharan Cc: Catalin Marinas , Will Deacon , Jonathan Corbet , Marc Zyngier , Rob Herring , Andre Przywara , Oliver Upton , "moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)" , "open list:DOCUMENTATION" , open list , stable@vger.kernel.org Subject: Re: [PATCH v2] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata Message-ID: References: <20240214175522.2457857-1-eahariha@linux.microsoft.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240214175522.2457857-1-eahariha@linux.microsoft.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240214_101505_998283_CFC299B4 X-CRM114-Status: GOOD ( 17.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Feb 14, 2024 at 05:55:18PM +0000, Easwar Hariharan wrote: > Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft > implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore > suffers from all the same errata. > > CC: stable@vger.kernel.org # 5.15+ > Signed-off-by: Easwar Hariharan Acked-by: Mark Rutland I assume that Catalin/Will will take this through the arm64 tree. Mark. > --- > changelog: > v1->v2: > * v1: https://lore.kernel.org/linux-arm-kernel/20240212232909.2276378-1-eahariha@linux.microsoft.com/T/#u > * Consistently use MICROSOFT throughout > --- > Documentation/arch/arm64/silicon-errata.rst | 7 +++++++ > arch/arm64/include/asm/cputype.h | 4 ++++ > arch/arm64/kernel/cpu_errata.c | 3 +++ > 3 files changed, 14 insertions(+) > > diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst > index e8c2ce1f9df6..45a7f4932fe0 100644 > --- a/Documentation/arch/arm64/silicon-errata.rst > +++ b/Documentation/arch/arm64/silicon-errata.rst > @@ -243,3 +243,10 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | ASR | ASR8601 | #8601001 | N/A | > +----------------+-----------------+-----------------+-----------------------------+ > ++----------------+-----------------+-----------------+-----------------------------+ > +| Microsoft | Azure Cobalt 100| #2139208 | ARM64_ERRATUM_2139208 | > ++----------------+-----------------+-----------------+-----------------------------+ > +| Microsoft | Azure Cobalt 100| #2067961 | ARM64_ERRATUM_2067961 | > ++----------------+-----------------+-----------------+-----------------------------+ > +| Microsoft | Azure Cobalt 100| #2253138 | ARM64_ERRATUM_2253138 | > ++----------------+-----------------+-----------------+-----------------------------+ > diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h > index 7c7493cb571f..52f076afeb96 100644 > --- a/arch/arm64/include/asm/cputype.h > +++ b/arch/arm64/include/asm/cputype.h > @@ -61,6 +61,7 @@ > #define ARM_CPU_IMP_HISI 0x48 > #define ARM_CPU_IMP_APPLE 0x61 > #define ARM_CPU_IMP_AMPERE 0xC0 > +#define ARM_CPU_IMP_MICROSOFT 0x6D > > #define ARM_CPU_PART_AEM_V8 0xD0F > #define ARM_CPU_PART_FOUNDATION 0xD00 > @@ -135,6 +136,8 @@ > > #define AMPERE_CPU_PART_AMPERE1 0xAC3 > > +#define MICROSOFT_CPU_PART_AZURE_COBALT_100 0xD49 /* Based on r0p0 of ARM Neoverse N2 */ > + > #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) > #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) > #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) > @@ -193,6 +196,7 @@ > #define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX) > #define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX) > #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1) > +#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100) > > /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */ > #define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index 967c7c7a4e7d..76b8dd37092a 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -374,6 +374,7 @@ static const struct midr_range erratum_1463225[] = { > static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { > #ifdef CONFIG_ARM64_ERRATUM_2139208 > MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), > + MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), > #endif > #ifdef CONFIG_ARM64_ERRATUM_2119858 > MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), > @@ -387,6 +388,7 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { > static const struct midr_range tsb_flush_fail_cpus[] = { > #ifdef CONFIG_ARM64_ERRATUM_2067961 > MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), > + MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), > #endif > #ifdef CONFIG_ARM64_ERRATUM_2054223 > MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), > @@ -399,6 +401,7 @@ static const struct midr_range tsb_flush_fail_cpus[] = { > static struct midr_range trbe_write_out_of_range_cpus[] = { > #ifdef CONFIG_ARM64_ERRATUM_2253138 > MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), > + MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100), > #endif > #ifdef CONFIG_ARM64_ERRATUM_2224489 > MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), > -- > 2.34.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel