From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0D249C4829E for ; Mon, 12 Feb 2024 23:44:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=bYtpsCKYXxKszuw1NClDkmeqe1+yEqcFW8+6YEH1EC4=; b=YcI0Fqd216ayzk MNFzwetDoSXSUQgspoz9OzNKjlSsE9qa2dENIVh43I3KmgeAylJ7WV2u7ak3VKQMC8B3UXVQgwVmk p6Gwta4Rh1a2ClzDKQm6VPs6szCCYfvS6mVfKVfiZhA3/z0TBq4bUk4UPRLAZz08xN15EJAfE3bxI BB7yHfTKyHw+oQW2lx8zjfD/tcwWnHDVtfZkTMxLQqq5NKG1yV7mOskAg1Edp5SNm3dZAhHJ3rX+v 4IRjNCe9mLecKJqDZCq6IezYYFwzY3BjjaUx91PcYIJeDvNJY2LYpTryXk1ybggCe+JT2oxpuJoWe FysfwvSuad9I+45rXP9Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rZfyd-00000007JtG-0tfX; Mon, 12 Feb 2024 23:44:43 +0000 Received: from out-172.mta0.migadu.com ([2001:41d0:1004:224b::ac]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rZfyY-00000007Jry-2A41 for linux-arm-kernel@lists.infradead.org; Mon, 12 Feb 2024 23:44:42 +0000 Date: Mon, 12 Feb 2024 15:44:19 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1707781472; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=ZavUZpfe4iXVeRQFF+1YAOemYZZVmPWyKDi8FAoNTa0=; b=rUiMa8QsnFQtpiR5C1+Uh/5PkvOSlnbxRtk2SQk/Z8VQaTr2nGOj+Kf6LQkivTtOFVviOx GtgnjamJJ3OTOqokx2EVRawtG0F5T88rRMMmwZRO8BLNIPMXRuYGO00y68upFxf8CSktjH smPhG3fjddzVZacfdEptan3ZSePE3uY= X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: Oliver Upton To: Easwar Hariharan Cc: Catalin Marinas , Will Deacon , Jonathan Corbet , Marc Zyngier , Andre Przywara , Rob Herring , Zenghui Yu , Mark Rutland , "moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)" , "open list:DOCUMENTATION" , open list , Anshuman Khandual , stable@vger.kernel.org Subject: Re: [PATCH] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata Message-ID: References: <20240212232909.2276378-1-eahariha@linux.microsoft.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240212232909.2276378-1-eahariha@linux.microsoft.com> X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240212_154440_994742_87546D81 X-CRM114-Status: GOOD ( 13.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Easwar, On Mon, Feb 12, 2024 at 11:29:06PM +0000, Easwar Hariharan wrote: > Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft > implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore > suffers from all the same errata. Can you comment at all on where one might find this MIDR? That is, does your hypervisor report the native MIDR of the implementation or does it repaint it as an Arm Neoverse N2 (0x410FD490)? > diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h > index 7c7493cb571f..a632a7514e55 100644 > --- a/arch/arm64/include/asm/cputype.h > +++ b/arch/arm64/include/asm/cputype.h > @@ -61,6 +61,7 @@ > #define ARM_CPU_IMP_HISI 0x48 > #define ARM_CPU_IMP_APPLE 0x61 > #define ARM_CPU_IMP_AMPERE 0xC0 > +#define ARM_CPU_IMP_MICROSOFT 0x6D > > #define ARM_CPU_PART_AEM_V8 0xD0F > #define ARM_CPU_PART_FOUNDATION 0xD00 > @@ -135,6 +136,8 @@ > > #define AMPERE_CPU_PART_AMPERE1 0xAC3 > > +#define MSFT_CPU_PART_AZURE_COBALT_100 0xD49 /* Based on r0p0 of ARM Neoverse N2 */ > + > #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) > #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) > #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) > @@ -193,6 +196,7 @@ > #define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX) > #define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX) > #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1) > +#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MSFT_CPU_PART_AZURE_COBALT_100) nitpick: consistently use the abbreviated 'MSFT' for all the definitions you're adding. -- Thanks, Oliver _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel