From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E364BC48260 for ; Tue, 13 Feb 2024 10:39:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9sRVuwy/jtfIZBOHvTanIN3FYKBAD0I7wAcnIslBMdQ=; b=m2nuxf285BEQJf cIBaZNVqvc1t++GuTaCrb4NGK4u/hoF3sCw3/AXURoaXARZDURcEeYoY/bfINBjCR7pb1ZBqk6vyB L34huRVkTiHo1ph4tEf6I1XDdbZcSh1dn34PAeFTiWNSD/pT/Z58DHIoZamICdF4lD6nNBUeB2Gqx kSLUvJgOB3U11zYUvXvTcSWEZXWYkDEIBpeKo/UJHM+Fzjy1MjpoZyGTnymqZ/zJkzEC/NFGMJrYK iXRi/m0CMjICVDh6xyAXH9ZVInBlfMeM6q47MwbJb/UCQOdoMdSC2sbgzOPU8QW53CkL3F6BeU+yd fXx89prOM4XE7gMg5G7Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rZqBk-00000008rdV-01s3; Tue, 13 Feb 2024 10:38:56 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rZqBg-00000008rc9-0kPq for linux-arm-kernel@lists.infradead.org; Tue, 13 Feb 2024 10:38:54 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 145016136F; Tue, 13 Feb 2024 10:38:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0DC26C43390; Tue, 13 Feb 2024 10:38:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1707820730; bh=WcE4bpvmsl5VfCuHe/MlIkl5JrTCTkvLgvaxBT5+0Fc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=aJ9quviDphi5o+aM4hVS76ZVdjose712xI0E9nXVkhvB6497uUXsDb/FOszQu1i1j qMDzeIS8RJBngLTcqAESIuMb6b1BZ2/cG/aEla6peQLWT/46LiJe38ZEqlD9I4CbWR clOqbsgZjdY6aJix4oro1B+kEyOWrT5pnpIW1ogf7AkLb+MOnqlDfXL7WXDHo/WcZ5 rG52yqBH1JklZr6fM9f4smFdXiDZdcrnNLJXqxO0uopEkR3wNgyHUInZ20kzN0pf4/ df7wPXg5F3j/iIHt58IJtPVH4JhDrfTgD39MmbrG8mWxd8+m1r2WV/tJtKS4bGk6zM TyMoCiba808eg== Date: Tue, 13 Feb 2024 11:38:43 +0100 From: Lorenzo Pieralisi To: Frank Li Cc: manivannan.sadhasivam@linaro.org, bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, krzysztof.kozlowski@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, robh@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org, hch@lst.de, robin.murphy@arm.com Subject: Re: [PATCH v9 16/16] PCI: imx6: Add iMX95 Endpoint (EP) support Message-ID: References: <20240119171122.3057511-1-Frank.Li@nxp.com> <20240119171122.3057511-17-Frank.Li@nxp.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240119171122.3057511-17-Frank.Li@nxp.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240213_023852_380817_E4134998 X-CRM114-Status: GOOD ( 25.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org [+Christoph, Robin - just checking with you if the DMA mask handling is what you expect from drivers, don't want to merge code that breaks your expectations] On Fri, Jan 19, 2024 at 12:11:22PM -0500, Frank Li wrote: > Add iMX95 EP support and add 64bit address support. Internal bus bridge for > PCI support 64bit dma address in iMX95. Hence, call > dma_set_mask_and_coherent() to set 64 bit DMA mask. > > Reviewed-by: Manivannan Sadhasivam > Signed-off-by: Frank Li > --- > > Notes: > Change from v8 to v9 > - update fixme comments > - update BAR1 comments > - Add mani's review tag > Change from v7 to v8 > - Update commit message > - Using Fixme > - Update clks_cnts by ARRAY_SIZE > > Change from v4 to v7 > - none > Change from v3 to v4 > - change align to 4k for imx95 > Change from v1 to v3 > - new patches at v3 > > drivers/pci/controller/dwc/pci-imx6.c | 47 +++++++++++++++++++++++++++ > 1 file changed, 47 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index bbaa45c08323b..7889318f6555a 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -75,6 +75,7 @@ enum imx6_pcie_variants { > IMX8MQ_EP, > IMX8MM_EP, > IMX8MP_EP, > + IMX95_EP, > }; > > #define IMX6_PCIE_FLAG_IMX6_PHY BIT(0) > @@ -84,6 +85,7 @@ enum imx6_pcie_variants { > #define IMX6_PCIE_FLAG_HAS_APP_RESET BIT(4) > #define IMX6_PCIE_FLAG_HAS_PHY_RESET BIT(5) > #define IMX6_PCIE_FLAG_HAS_SERDES BIT(6) > +#define IMX6_PCIE_FLAG_SUPPORT_64BIT BIT(7) > > #define imx6_check_flag(pci, val) (pci->drvdata->flags & val) > > @@ -616,6 +618,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) > break; > case IMX7D: > case IMX95: > + case IMX95_EP: > break; > case IMX8MM: > case IMX8MM_EP: > @@ -1050,6 +1053,23 @@ static const struct pci_epc_features imx8m_pcie_epc_features = { > .align = SZ_64K, > }; > > +/* > + * BAR# | Default BAR enable | Default BAR Type | Default BAR Size | BAR Sizing Scheme > + * ================================================================================================ > + * BAR0 | Enable | 64-bit | 1 MB | Programmable Size > + * BAR1 | Disable | 32-bit | 64 KB | Fixed Size > + * BAR1 should be disabled if BAR0 is 64bit. > + * BAR2 | Enable | 32-bit | 1 MB | Programmable Size > + * BAR3 | Enable | 32-bit | 64 KB | Programmable Size > + * BAR4 | Enable | 32-bit | 1M | Programmable Size > + * BAR5 | Enable | 32-bit | 64 KB | Programmable Size > + */ > +static const struct pci_epc_features imx95_pcie_epc_features = { > + .msi_capable = true, > + .bar_fixed_size[1] = SZ_64K, > + .align = SZ_4K, > +}; > + > static const struct pci_epc_features* > imx6_pcie_ep_get_features(struct dw_pcie_ep *ep) > { > @@ -1092,6 +1112,15 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie, > > pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset; > > + /* > + * FIXME: Ideally, dbi2 base address should come from DT. But since only IMX95 is defining > + * "dbi2" in DT, "dbi_base2" is set to NULL here for that platform alone so that the DWC > + * core code can fetch that from DT. But once all platform DTs were fixed, this and the > + * above "dbi_base2" setting should be removed. > + */ > + if (imx6_pcie->drvdata->variant == IMX95_EP) > + pci->dbi_base2 = NULL; > + > ret = dw_pcie_ep_init(ep); > if (ret) { > dev_err(dev, "failed to initialize endpoint\n"); > @@ -1345,6 +1374,9 @@ static int imx6_pcie_probe(struct platform_device *pdev) > "unable to find iomuxc registers\n"); > } > > + if (imx6_check_flag(imx6_pcie, IMX6_PCIE_FLAG_SUPPORT_64BIT)) > + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); > + > /* Grab PCIe PHY Tx Settings */ > if (of_property_read_u32(node, "fsl,tx-deemph-gen1", > &imx6_pcie->tx_deemph_gen1)) > @@ -1563,6 +1595,20 @@ static const struct imx6_pcie_drvdata drvdata[] = { > .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, > .epc_features = &imx8m_pcie_epc_features, > }, > + [IMX95_EP] = { > + .variant = IMX95_EP, > + .flags = IMX6_PCIE_FLAG_HAS_SERDES | > + IMX6_PCIE_FLAG_SUPPORT_64BIT, > + .clk_names = imx8mq_clks, > + .clks_cnt = ARRAY_SIZE(imx8mq_clks), > + .ltssm_off = IMX95_PE0_GEN_CTRL_3, > + .ltssm_mask = IMX95_PCIE_LTSSM_EN, > + .mode_off[0] = IMX95_PE0_GEN_CTRL_1, > + .mode_mask[0] = IMX95_PCIE_DEVICE_TYPE, > + .init_phy = imx95_pcie_init_phy, > + .epc_features = &imx95_pcie_epc_features, > + .mode = DW_PCIE_EP_TYPE, > + }, > }; > > static const struct of_device_id imx6_pcie_of_match[] = { > @@ -1577,6 +1623,7 @@ static const struct of_device_id imx6_pcie_of_match[] = { > { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], }, > { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], }, > { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], }, > + { .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], }, > {}, > }; > > -- > 2.34.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel