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[34.140.83.185]) by smtp.gmail.com with ESMTPSA id jx6-20020a05600c578600b0040ffd94cd27sm11909083wmb.45.2024.02.13.07.40.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Feb 2024 07:40:38 -0800 (PST) Date: Tue, 13 Feb 2024 15:40:34 +0000 From: Mostafa Saleh To: Jason Gunthorpe Cc: iommu@lists.linux.dev, Joerg Roedel , linux-arm-kernel@lists.infradead.org, Robin Murphy , Will Deacon , Lu Baolu , Jean-Philippe Brucker , Joerg Roedel , Moritz Fischer , Moritz Fischer , Michael Shavit , Nicolin Chen , patches@lists.linux.dev, Shameer Kolothum , Zhangfei Gao Subject: Re: [PATCH v5 08/17] iommu/arm-smmu-v3: Do not change the STE twice during arm_smmu_attach_dev() Message-ID: References: <0-v5-cd1be8dd9c71+3fa-smmuv3_newapi_p1_jgg@nvidia.com> <8-v5-cd1be8dd9c71+3fa-smmuv3_newapi_p1_jgg@nvidia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <8-v5-cd1be8dd9c71+3fa-smmuv3_newapi_p1_jgg@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240213_074041_065955_913C13AE X-CRM114-Status: GOOD ( 31.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Jason, On Tue, Feb 06, 2024 at 11:12:45AM -0400, Jason Gunthorpe wrote: > This was needed because the STE code required the STE to be in > ABORT/BYPASS inorder to program a cdtable or S2 STE. Now that the STE code > can automatically handle all transitions we can remove this step > from the attach_dev flow. > > A few small bugs exist because of this: > > 1) If the core code does BLOCKED -> UNMANAGED with disable_bypass=false > then there will be a moment where the STE points at BYPASS. Since > this can be done by VFIO/IOMMUFD it is a small security race. > > 2) If the core code does IDENTITY -> DMA then any IOMMU_RESV_DIRECT > regions will temporarily become BLOCKED. We'd like drivers to > work in a way that allows IOMMU_RESV_DIRECT to be continuously > functional during these transitions. > > Make arm_smmu_release_device() put the STE back to the correct > ABORT/BYPASS setting. Fix a bug where a IOMMU_RESV_DIRECT was ignored on > this path. > > As noted before the reordering of the linked list/STE/CD changes is OK > against concurrent arm_smmu_share_asid() because of the > arm_smmu_asid_lock. > > Tested-by: Shameer Kolothum > Tested-by: Nicolin Chen > Tested-by: Moritz Fischer > Reviewed-by: Nicolin Chen > Signed-off-by: Jason Gunthorpe > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 15 +++++++++------ > 1 file changed, 9 insertions(+), 6 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index 1138e868c4d73e..340f3dc82c9ce0 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -2562,7 +2562,6 @@ static void arm_smmu_disable_pasid(struct arm_smmu_master *master) > static void arm_smmu_detach_dev(struct arm_smmu_master *master) > { > unsigned long flags; > - struct arm_smmu_ste target; > struct arm_smmu_domain *smmu_domain = master->domain; > > if (!smmu_domain) > @@ -2576,11 +2575,6 @@ static void arm_smmu_detach_dev(struct arm_smmu_master *master) > > master->domain = NULL; > master->ats_enabled = false; > - if (disable_bypass) > - arm_smmu_make_abort_ste(&target); > - else > - arm_smmu_make_bypass_ste(&target); > - arm_smmu_install_ste_for_dev(master, &target); > /* > * Clearing the CD entry isn't strictly required to detach the domain > * since the table is uninstalled anyway, but it helps avoid confusion > @@ -2928,9 +2922,18 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev) > static void arm_smmu_release_device(struct device *dev) > { > struct arm_smmu_master *master = dev_iommu_priv_get(dev); > + struct arm_smmu_ste target; > > if (WARN_ON(arm_smmu_master_sva_enabled(master))) > iopf_queue_remove_device(master->smmu->evtq.iopf, dev); > + > + /* Put the STE back to what arm_smmu_init_strtab() sets */ > + if (disable_bypass && !dev->iommu->require_direct) > + arm_smmu_make_abort_ste(&target); > + else > + arm_smmu_make_bypass_ste(&target); > + arm_smmu_install_ste_for_dev(master, &target); > + > arm_smmu_detach_dev(master); > arm_smmu_disable_pasid(master); > arm_smmu_remove_master(master); > -- > 2.43.0 > I am still reviewing patch-1 and the hitless machinery (also I think -or hope- this can be simplified), with the assumption that arm_smmu_install_ste_for_dev()/arm_smmu_write_ste() will do the right thing, that good looks good to me. However, as it changes the current behavior of the driver where disable_bypass used to override require_direct, I am not sure if this would break any existing setups. Thanks, Mostafa _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel