From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5CF50C54798 for ; Tue, 27 Feb 2024 10:06:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=mxOJozSKl80l2bqldnV+37zXBHJ+B6ELTuxfe7w+sT0=; b=00/m3ZmNy88uhd 9qeMKSOjZY7BqpYSpmJNskIubTyPbEIxnK8kdVBchyRJ8iCYntRnrs2E1Dgk1sXMAMfcThMk/++6f efQS3eCB02C0OCb5i5+sYoQESLpdBd+5Zzrrf2WMpycCTBmGqquLDB+bn4QtoxpcQRurFJCJXzNCj R99MDies/vhOiK4PTSfZcqTOEfDCpwBwQ9z5monVoIyrerRLHYo3JbQxU8uh3JMTm3lq6j/kqSVY9 PxXf0kNK+CXxe2Mt4DeOSTXSMliKeqaMJZUeolioaS4rkwBvA5NJ+FXx14gBk9UIXYYjJve2UikUo QQX0UZgqLPnYRmdNTNxQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1reuM0-00000004eKZ-1Pmq; Tue, 27 Feb 2024 10:06:28 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1reuLw-00000004eJi-49OL for linux-arm-kernel@lists.infradead.org; Tue, 27 Feb 2024 10:06:26 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8A2D4DA7; Tue, 27 Feb 2024 02:07:00 -0800 (PST) Received: from FVFF77S0Q05N (unknown [10.57.79.110]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EF23C3F762; Tue, 27 Feb 2024 02:06:20 -0800 (PST) Date: Tue, 27 Feb 2024 10:06:18 +0000 From: Mark Rutland To: Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org, broonie@kernel.org, Catalin Marinas , Will Deacon , Marc Zyngier , linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64/sysreg: Add BRBE registers and fields Message-ID: References: <20240125094119.2542332-2-anshuman.khandual@arm.com> <20240226042441.4098806-1-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240226042441.4098806-1-anshuman.khandual@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240227_020625_145493_796ED919 X-CRM114-Status: GOOD ( 20.82 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Feb 26, 2024 at 09:54:41AM +0530, Anshuman Khandual wrote: > This adds BRBE related register definitions and various other related field > macros there in. These will be used subsequently in a BRBE driver, which is > being added later on. While here, this drops redundant register definitions > from the header i.e (arch/arm64/include/asm/sysreg.h). > > BRBINFx_EL1_TYPE_IMPDEF_TRAP_EL3 register field value has been derived from > latest ARM DDI 0601 ID121123, AKA 2023-12 instead of latest ARM ARM i.e ARM > DDI 0487J.a. Please find the definition here. > > https://developer.arm.com/documentation/ddi0601/2023-12/ > > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Marc Zyngier > Cc: Mark Rutland > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Signed-off-by: Anshuman Khandual > --- > Please find the modified patch here for a quick review and do let me know > if this looks good for the next version i.e V17. BRBCR_EL1/12/2 organized > per their encoding. Thanks ! Superficially that looks fine to me. Mark. > arch/arm64/include/asm/sysreg.h | 17 ++--- > arch/arm64/tools/sysreg | 131 ++++++++++++++++++++++++++++++++ > 2 files changed, 137 insertions(+), 11 deletions(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index c3b19b376c86..481c7d186dfa 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -195,16 +195,8 @@ > #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0) > > #define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0)) > -#define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0) > #define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1)) > -#define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1) > #define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2)) > -#define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2) > -#define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2) > - > -#define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0) > -#define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1) > -#define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0) > > #define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3) > #define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3))) > @@ -270,8 +262,6 @@ > /* ETM */ > #define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4) > > -#define SYS_BRBCR_EL2 sys_reg(2, 4, 9, 0, 0) > - > #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) > #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) > #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) > @@ -601,7 +591,6 @@ > #define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2) > > /* VHE encodings for architectural EL0/1 system registers */ > -#define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0) > #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0) > #define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2) > #define SYS_SCTLR2_EL12 sys_reg(3, 5, 1, 0, 3) > @@ -794,6 +783,12 @@ > #define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6) > #define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7) > > +/* > + * BRBE Instructions > + */ > +#define BRB_IALL_INSN __emit_inst(0xd5000000 | OP_BRB_IALL | (0x1f)) > +#define BRB_INJ_INSN __emit_inst(0xd5000000 | OP_BRB_INJ | (0x1f)) > + > /* Common SCTLR_ELx flags. */ > #define SCTLR_ELx_ENTP2 (BIT(60)) > #define SCTLR_ELx_DSSBS (BIT(44)) > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > index 4c9b67934367..60d288cbd5eb 100644 > --- a/arch/arm64/tools/sysreg > +++ b/arch/arm64/tools/sysreg > @@ -1023,6 +1023,137 @@ UnsignedEnum 3:0 MTEPERM > EndEnum > EndSysreg > > + > +SysregFields BRBINFx_EL1 > +Res0 63:47 > +Field 46 CCU > +Field 45:32 CC > +Res0 31:18 > +Field 17 LASTFAILED > +Field 16 T > +Res0 15:14 > +Enum 13:8 TYPE > + 0b000000 DIRECT_UNCOND > + 0b000001 INDIRECT > + 0b000010 DIRECT_LINK > + 0b000011 INDIRECT_LINK > + 0b000101 RET > + 0b000111 ERET > + 0b001000 DIRECT_COND > + 0b100001 DEBUG_HALT > + 0b100010 CALL > + 0b100011 TRAP > + 0b100100 SERROR > + 0b100110 INSN_DEBUG > + 0b100111 DATA_DEBUG > + 0b101010 ALIGN_FAULT > + 0b101011 INSN_FAULT > + 0b101100 DATA_FAULT > + 0b101110 IRQ > + 0b101111 FIQ > + 0b110000 IMPDEF_TRAP_EL3 > + 0b111001 DEBUG_EXIT > +EndEnum > +Enum 7:6 EL > + 0b00 EL0 > + 0b01 EL1 > + 0b10 EL2 > + 0b11 EL3 > +EndEnum > +Field 5 MPRED > +Res0 4:2 > +Enum 1:0 VALID > + 0b00 NONE > + 0b01 TARGET > + 0b10 SOURCE > + 0b11 FULL > +EndEnum > +EndSysregFields > + > +SysregFields BRBCR_ELx > +Res0 63:24 > +Field 23 EXCEPTION > +Field 22 ERTN > +Res0 21:10 > +Field 9 FZPSS > +Field 8 FZP > +Res0 7 > +Enum 6:5 TS > + 0b01 VIRTUAL > + 0b10 GUEST_PHYSICAL > + 0b11 PHYSICAL > +EndEnum > +Field 4 MPRED > +Field 3 CC > +Res0 2 > +Field 1 ExBRE > +Field 0 E0BRE > +EndSysregFields > + > +Sysreg BRBCR_EL1 2 1 9 0 0 > +Fields BRBCR_ELx > +EndSysreg > + > +Sysreg BRBFCR_EL1 2 1 9 0 1 > +Res0 63:30 > +Enum 29:28 BANK > + 0b00 BANK_0 > + 0b01 BANK_1 > +EndEnum > +Res0 27:23 > +Field 22 CONDDIR > +Field 21 DIRCALL > +Field 20 INDCALL > +Field 19 RTN > +Field 18 INDIRECT > +Field 17 DIRECT > +Field 16 EnI > +Res0 15:8 > +Field 7 PAUSED > +Field 6 LASTFAILED > +Res0 5:0 > +EndSysreg > + > +Sysreg BRBTS_EL1 2 1 9 0 2 > +Field 63:0 TS > +EndSysreg > + > +Sysreg BRBINFINJ_EL1 2 1 9 1 0 > +Fields BRBINFx_EL1 > +EndSysreg > + > +Sysreg BRBSRCINJ_EL1 2 1 9 1 1 > +Field 63:0 ADDRESS > +EndSysreg > + > +Sysreg BRBTGTINJ_EL1 2 1 9 1 2 > +Field 63:0 ADDRESS > +EndSysreg > + > +Sysreg BRBIDR0_EL1 2 1 9 2 0 > +Res0 63:16 > +Enum 15:12 CC > + 0b101 20_BIT > +EndEnum > +Enum 11:8 FORMAT > + 0b0 0 > +EndEnum > +Enum 7:0 NUMREC > + 0b00001000 8 > + 0b00010000 16 > + 0b00100000 32 > + 0b01000000 64 > +EndEnum > +EndSysreg > + > +Sysreg BRBCR_EL2 2 4 9 0 0 > +Fields BRBCR_ELx > +EndSysreg > + > +Sysreg BRBCR_EL12 2 5 9 0 0 > +Fields BRBCR_ELx > +EndSysreg > + > Sysreg ID_AA64ZFR0_EL1 3 0 0 4 4 > Res0 63:60 > UnsignedEnum 59:56 F64MM > -- > 2.25.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel