[PATCH] arm64/hw_breakpoint: Define an ISS code for watchpoint exception

[PATCH] arm64/hw_breakpoint: Define an ISS code for watchpoint exception

[Anshuman Khandual]

This defines a new ISS code macro i.e ESR_ELx_WnR for watchpoint exception.
This represents an instruction's either writing to or reading from a memory
location during an watchpoint exception, and also moves this macro into the
ESR header as required. This drops non-standard AARCH64_ESR_ACCESS_MASK.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
This applies on v6.8-rc5

 arch/arm64/include/asm/esr.h           | 4 ++++
 arch/arm64/include/asm/hw_breakpoint.h | 1 -
 arch/arm64/kernel/hw_breakpoint.c      | 3 ++-
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
index 353fe08546cf..6c0a0b77fd2c 100644
--- a/arch/arm64/include/asm/esr.h
+++ b/arch/arm64/include/asm/esr.h
@@ -143,6 +143,10 @@
 #define ESR_ELx_CM_SHIFT	(8)
 #define ESR_ELx_CM 		(UL(1) << ESR_ELx_CM_SHIFT)
 
+/* ISS field definitions for Watchpoint exception */
+#define ESR_ELx_WnR_SHIFT	(6)
+#define ESR_ELx_WnR		(UL(1) << ESR_ELx_WnR_SHIFT)
+
 /* ISS2 field definitions for Data Aborts */
 #define ESR_ELx_TnD_SHIFT	(10)
 #define ESR_ELx_TnD 		(UL(1) << ESR_ELx_TnD_SHIFT)
diff --git a/arch/arm64/include/asm/hw_breakpoint.h b/arch/arm64/include/asm/hw_breakpoint.h
index d67c02e53a4a..6e4862e3d238 100644
--- a/arch/arm64/include/asm/hw_breakpoint.h
+++ b/arch/arm64/include/asm/hw_breakpoint.h
@@ -67,7 +67,6 @@ static inline void decode_ctrl_reg(u32 reg,
 /* Watchpoints */
 #define ARM_BREAKPOINT_LOAD	1
 #define ARM_BREAKPOINT_STORE	2
-#define AARCH64_ESR_ACCESS_MASK	(1 << 6)
 
 /* Lengths */
 #define ARM_BREAKPOINT_LEN_1	0x1
diff --git a/arch/arm64/kernel/hw_breakpoint.c b/arch/arm64/kernel/hw_breakpoint.c
index 86bdb2d68732..a73364a18c69 100644
--- a/arch/arm64/kernel/hw_breakpoint.c
+++ b/arch/arm64/kernel/hw_breakpoint.c
@@ -21,6 +21,7 @@
 
 #include <asm/current.h>
 #include <asm/debug-monitors.h>
+#include <asm/esr.h>
 #include <asm/hw_breakpoint.h>
 #include <asm/traps.h>
 #include <asm/cputype.h>
@@ -792,7 +793,7 @@ static int watchpoint_handler(unsigned long addr, unsigned long esr,
 		 * Check that the access type matches.
 		 * 0 => load, otherwise => store
 		 */
-		access = (esr & AARCH64_ESR_ACCESS_MASK) ? HW_BREAKPOINT_W :
+		access = (esr & ESR_ELx_WnR) ? HW_BREAKPOINT_W :
 			 HW_BREAKPOINT_R;
 		if (!(access & hw_breakpoint_type(wp)))
 			continue;
-- 
2.25.1


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Re: [PATCH] arm64/hw_breakpoint: Define an ISS code for watchpoint exception

[Mark Brown]

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On Fri, Feb 23, 2024 at 03:16:15PM +0530, Anshuman Khandual wrote:
> This defines a new ISS code macro i.e ESR_ELx_WnR for watchpoint exception.
> This represents an instruction's either writing to or reading from a memory
> location during an watchpoint exception, and also moves this macro into the
> ESR header as required. This drops non-standard AARCH64_ESR_ACCESS_MASK.

Reviewed-by: Mark Brown <broonie@kernel.org>

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Re: [PATCH] arm64/hw_breakpoint: Define an ISS code for watchpoint exception

[Catalin Marinas]

On Fri, Feb 23, 2024 at 03:16:15PM +0530, Anshuman Khandual wrote:
> diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
> index 353fe08546cf..6c0a0b77fd2c 100644
> --- a/arch/arm64/include/asm/esr.h
> +++ b/arch/arm64/include/asm/esr.h
> @@ -143,6 +143,10 @@
>  #define ESR_ELx_CM_SHIFT	(8)
>  #define ESR_ELx_CM 		(UL(1) << ESR_ELx_CM_SHIFT)
>  
> +/* ISS field definitions for Watchpoint exception */
> +#define ESR_ELx_WnR_SHIFT	(6)
> +#define ESR_ELx_WnR		(UL(1) << ESR_ELx_WnR_SHIFT)

We had ESR_ELx_WNR since about 2015, maybe even earlier in the form of
EL1 or EL2. Only that the 'n' is uppercase. So please use that, don't
add a new definition.

-- 
Catalin

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Re: [PATCH] arm64/hw_breakpoint: Define an ISS code for watchpoint exception

[Anshuman Khandual]

On 2/28/24 20:59, Catalin Marinas wrote:
> On Fri, Feb 23, 2024 at 03:16:15PM +0530, Anshuman Khandual wrote:
>> diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
>> index 353fe08546cf..6c0a0b77fd2c 100644
>> --- a/arch/arm64/include/asm/esr.h
>> +++ b/arch/arm64/include/asm/esr.h
>> @@ -143,6 +143,10 @@
>>  #define ESR_ELx_CM_SHIFT	(8)
>>  #define ESR_ELx_CM 		(UL(1) << ESR_ELx_CM_SHIFT)
>>  
>> +/* ISS field definitions for Watchpoint exception */
>> +#define ESR_ELx_WnR_SHIFT	(6)
>> +#define ESR_ELx_WnR		(UL(1) << ESR_ELx_WnR_SHIFT)
> 
> We had ESR_ELx_WNR since about 2015, maybe even earlier in the form of
> EL1 or EL2. Only that the 'n' is uppercase. So please use that, don't
> add a new definition.

Right, reusing existing ESR_ELx_WNR makes sense, will respin the patch.

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