From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B500DC5475B for ; Fri, 1 Mar 2024 18:52:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=1WplqFV2w58yBUM9SbyUa0CNtX15Fcsw7Eim2NMjWSE=; b=RgEkk6K+vSsCoB YxtiCGpNsk3Jc9xXNuls0k+RuSNyeDqmm79pbCVzL/d6mK6lc7vf0O6kTsVX5xcGp3mclzApQGAFo onLnGXMwjcQC/s01OXgklwtCCrvVjdeB+r+03CCWz7N/Lzb2yCGxbcvW8qsnCIZhEcnsGZZPe6s3P WF7mHiZk5+PfpHtpgi0GjYKmcm5upg7pxZn6cbArdqbdFfn23EL4h+QMb7cvDSQWTOw0zGjb/zi42 NuERw/r3aC4JyBKXj16AM4vdkik+eQ3Y6rOVIpcWE8hTEvzuolDMN3x/n3M0TR8Pbn8D5wcmDCb8v P0qWUAO4P2QI1sPkW1pg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rg7zz-00000001bVH-0jOr; Fri, 01 Mar 2024 18:52:47 +0000 Received: from sin.source.kernel.org ([145.40.73.55]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rg7zw-00000001bTH-0She for linux-arm-kernel@lists.infradead.org; Fri, 01 Mar 2024 18:52:45 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by sin.source.kernel.org (Postfix) with ESMTP id 71A33CE26EA; Fri, 1 Mar 2024 18:52:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 04C1AC433F1; Fri, 1 Mar 2024 18:52:34 +0000 (UTC) Date: Fri, 1 Mar 2024 18:52:32 +0000 From: Catalin Marinas To: Jason Gunthorpe Cc: Alexander Gordeev , Andrew Morton , Christian Borntraeger , Borislav Petkov , Dave Hansen , "David S. Miller" , Eric Dumazet , Gerald Schaefer , Vasily Gorbik , Heiko Carstens , "H. Peter Anvin" , Justin Stitt , Jakub Kicinski , Leon Romanovsky , linux-rdma@vger.kernel.org, linux-s390@vger.kernel.org, llvm@lists.linux.dev, Ingo Molnar , Bill Wendling , Nathan Chancellor , Nick Desaulniers , netdev@vger.kernel.org, Paolo Abeni , Salil Mehta , Jijie Shao , Sven Schnelle , Thomas Gleixner , x86@kernel.org, Yisen Zhuang , Arnd Bergmann , Leon Romanovsky , linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Mark Rutland , Michael Guralnik , patches@lists.linux.dev, Niklas Schnelle , Will Deacon Subject: Re: [PATCH 4/6] arm64/io: Provide a WC friendly __iowriteXX_copy() Message-ID: References: <0-v1-38290193eace+5-mlx5_arm_wc_jgg@nvidia.com> <4-v1-38290193eace+5-mlx5_arm_wc_jgg@nvidia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <4-v1-38290193eace+5-mlx5_arm_wc_jgg@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240301_105244_521740_98235841 X-CRM114-Status: GOOD ( 20.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Feb 20, 2024 at 09:17:08PM -0400, Jason Gunthorpe wrote: > The kernel provides driver support for using write combining IO memory > through the __iowriteXX_copy() API which is commonly used as an optional > optimization to generate 16/32/64 byte MemWr TLPs in a PCIe environment. > > iomap_copy.c provides a generic implementation as a simple 4/8 byte at a > time copy loop that has worked well with past ARM64 CPUs, giving a high > frequency of large TLPs being successfully formed. > > However modern ARM64 CPUs are quite sensitive to how the write combining > CPU HW is operated and a compiler generated loop with intermixed > load/store is not sufficient to frequently generate a large TLP. The CPUs > would like to see the entire TLP generated by consecutive store > instructions from registers. Compilers like gcc tend to intermix loads and > stores and have poor code generation, in part, due to the ARM64 situation > that writeq() does not codegen anything other than "[xN]". However even > with that resolved compilers like clang still do not have good code > generation. > > This means on modern ARM64 CPUs the rate at which __iowriteXX_copy() > successfully generates large TLPs is very small (less than 1 in 10,000) > tries), to the point that the use of WC is pointless. > > Implement __iowrite32/64_copy() specifically for ARM64 and use inline > assembly to build consecutive blocks of STR instructions. Provide direct > support for 64/32/16 large TLP generation in this manner. Optimize for > common constant lengths so that the compiler can directly inline the store > blocks. > > This brings the frequency of large TLP generation up to a high level that > is comparable with older CPU generations. > > As the __iowriteXX_copy() family of APIs is intended for use with WC > incorporate the DGH hint directly into the function. > > Cc: Arnd Bergmann > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Mark Rutland > Cc: linux-arch@vger.kernel.org > Cc: linux-arm-kernel@lists.infradead.org > Signed-off-by: Jason Gunthorpe Apart from the slightly more complicated code, I don't expect it to make things worse on any of the existing hardware. So, with the typo fix that Will mentioned: Reviewed-by: Catalin Marinas _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel