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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Mar 07, 2024 at 08:22:25AM +0100, Alexander Stein wrote: > Hi Frank, > = > Am Mittwoch, 6. M=E4rz 2024, 16:19:18 CET schrieb Frank Li: > > On Wed, Mar 06, 2024 at 08:20:00AM +0100, Alexander Stein wrote: > > > Hi Frank, > > > = > > > thanks for the patch. > > > = > > > Am Dienstag, 5. M=E4rz 2024, 18:33:05 CET schrieb Frank Li: > > > > Add asrc[0,1], esai0, spdif[0,1], sai[4,5] and related lpcg node for > > > > imx8 audio subsystem. > > > > = > > > > Signed-off-by: Frank Li > > > > --- > > > > arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi | 304 +++++++++++= ++++++++++++ > > > > 1 file changed, 304 insertions(+) > > > > = > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arc= h/arm64/boot/dts/freescale/imx8-ss-audio.dtsi > > > > index 07afeb78ed564..78305559f15c9 100644 > > > > --- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi > > > > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi > > > > @@ -6,6 +6,7 @@ > > > > = > > > > #include > > > > #include > > > > +#include > > > > #include > > > > = > > > > audio_ipg_clk: clock-audio-ipg { > > > > @@ -481,4 +482,307 @@ acm: acm@59e00000 { > > > > "sai3_rx_bclk", > > > > "sai4_rx_bclk"; > > > > }; > > > > + > > > > + asrc0: asrc@59000000 { > > > = > > > Please insert nodes sorted by address. ASRC0 is the very first node. > > > = > > > > + compatible =3D "fsl,imx8qm-asrc"; > > > > + reg =3D <0x59000000 0x10000>; > > > > + interrupts =3D ; > > > > + clocks =3D <&asrc0_lpcg 0>, > > > > + <&asrc0_lpcg 0>, > > > > + <&aud_pll_div0_lpcg 0>, > > > > + <&aud_pll_div1_lpcg 0>, > > > > + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, > > > > + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>; > > > > + clock-names =3D "mem", "ipg", > > > > + "asrck_0", "asrck_1", "asrck_2", "asrck_3", > > > > + "asrck_4", "asrck_5", "asrck_6", "asrck_7", > > > > + "asrck_8", "asrck_9", "asrck_a", "asrck_b", > > > > + "asrck_c", "asrck_d", "asrck_e", "asrck_f", > > > > + "spba"; > > > > + dmas =3D <&edma0 0 0 0>, > > > > + <&edma0 1 0 0>, > > > > + <&edma0 2 0 0>, > > > > + <&edma0 3 0 FSL_EDMA_RX>, > > > > + <&edma0 4 0 FSL_EDMA_RX>, > > > > + <&edma0 5 0 FSL_EDMA_RX>; > > > > + /* tx* is output channel of asrc, it is rx channel for eDMA */ > > > > + dma-names =3D "rxa", "rxb", "rxc", "txa", "txb", "txc"; > > > > + fsl,asrc-rate =3D <8000>; > > > > + fsl,asrc-width =3D <16>; > > > > + fsl,asrc-clk-map =3D <0>; > > > > + power-domains =3D <&pd IMX_SC_R_ASRC_0>; > > > > + status =3D "disabled"; > > > > + }; > > > > + > > > > + esai0: esai@59010000 { > > > > + compatible =3D "fsl,imx8qm-esai", "fsl,imx6ull-esai"; > > > > + reg =3D <0x59010000 0x10000>; > > > > + interrupts =3D ; > > > > + clocks =3D <&esai0_lpcg 1>, <&esai0_lpcg 0>, <&esai0_lpcg 1>, <&= clk_dummy>; > > > > + clock-names =3D "core", "extal", "fsys", "spba"; > > > > + dmas =3D <&edma0 6 0 FSL_EDMA_RX>, <&edma0 7 0 0>; > > > > + dma-names =3D "rx", "tx"; > > > > + power-domains =3D <&pd IMX_SC_R_ESAI_0>; > > > > + status =3D "disabled"; > > > > + }; > > > > + > > > > + spdif0: spdif@59020000 { > > > > + compatible =3D "fsl,imx8qm-spdif"; > > > > + reg =3D <0x59020000 0x10000>; > > > > + interrupts =3D , /* rx */ > > > > + ; /* tx */ > > > > + clocks =3D <&spdif0_lpcg 1>, /* core */ > > > > + <&clk_dummy>, /* rxtx0 */ > > > > + <&spdif0_lpcg 0>, /* rxtx1 */ > > > > + <&clk_dummy>, /* rxtx2 */ > > > > + <&clk_dummy>, /* rxtx3 */ > > > > + <&clk_dummy>, /* rxtx4 */ > > > > + <&audio_ipg_clk>, /* rxtx5 */ > > > > + <&clk_dummy>, /* rxtx6 */ > > > > + <&clk_dummy>, /* rxtx7 */ > > > > + <&clk_dummy>; /* spba */ > > > > + clock-names =3D "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxt= x4", > > > > + "rxtx5", "rxtx6", "rxtx7", "spba"; > > > > + dmas =3D <&edma0 8 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>, > > > > + <&edma0 9 0 FSL_EDMA_MULTI_FIFO>; > > > > + dma-names =3D "rx", "tx"; > > > > + power-domains =3D <&pd IMX_SC_R_SPDIF_0>; > > > > + status =3D "disabled"; > > > > + }; > > > > + > > > > + spdif1: spdif@59030000 { > > > = > > > That's imx8qm only, no? > > = > > I am not sure what means. why do you think it is imx8qm only? It is for > > imx8qm, imx8qxp, imx8dxl. > = > According to Table- 2-6 (Audio DMA memory Map) in i.MX8X RM Rev. 0 05/202= 0, > the lasted one available on the webpage, address 0x59030000 is reserved. > I read that as there is no periphery available. This matches the feature = list > in 1.1.2 Features, where "1x SPDIF" is stated. > = > So spdif1 is only for imx8qm (no idea about imx8dxl though) and should be > listed in a file called imx8qm-ss-audio.dtsi which is only included in > imx8qm.dtsi. > = Thanks, I will do that. > Thanks and best regards > Alexander > = > > = > > Frank > > = > > > = > > > > + compatible =3D "fsl,imx8qm-spdif"; > > > > + reg =3D <0x59030000 0x10000>; > > > > + interrupts =3D , /* rx */ > > > > + ; /* tx */ > > > > + clocks =3D <&spdif1_lpcg 1>, /* core */ > > > > + <&clk_dummy>, /* rxtx0 */ > > > > + <&spdif1_lpcg 0>, /* rxtx1 */ > > > > + <&clk_dummy>, /* rxtx2 */ > > > > + <&clk_dummy>, /* rxtx3 */ > > > > + <&clk_dummy>, /* rxtx4 */ > > > > + <&audio_ipg_clk>, /* rxtx5 */ > > > > + <&clk_dummy>, /* rxtx6 */ > > > > + <&clk_dummy>, /* rxtx7 */ > > > > + <&clk_dummy>; /* spba */ > > > > + clock-names =3D "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxt= x4", > > > > + "rxtx5", "rxtx6", "rxtx7", "spba"; > > > > + dmas =3D <&edma0 10 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>, > > > > + <&edma0 11 0 FSL_EDMA_MULTI_FIFO>; > > > > + dma-names =3D "rx", "tx"; > > > > + power-domains =3D <&pd IMX_SC_R_SPDIF_1>; > > > > + status =3D "disabled"; > > > > + }; > > > > + > > > > + asrc1: asrc@59800000 { > > > = > > > Insert this between dsp and edma1, sorted by address. > > > = > > > > + compatible =3D "fsl,imx8qm-asrc"; > > > > + reg =3D <0x59800000 0x10000>; > > > > + interrupts =3D ; > > > > + clocks =3D <&asrc1_lpcg 0>, > > > > + <&asrc1_lpcg 0>, > > > > + <&aud_pll_div0_lpcg 0>, > > > > + <&aud_pll_div1_lpcg 0>, > > > > + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, > > > > + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>; > > > > + clock-names =3D "mem", "ipg", > > > > + "asrck_0", "asrck_1", "asrck_2", "asrck_3", > > > > + "asrck_4", "asrck_5", "asrck_6", "asrck_7", > > > > + "asrck_8", "asrck_9", "asrck_a", "asrck_b", > > > > + "asrck_c", "asrck_d", "asrck_e", "asrck_f", > > > > + "spba"; > > > > + dmas =3D <&edma1 0 0 0>, > > > > + <&edma1 1 0 0>, > > > > + <&edma1 2 0 0>, > > > > + <&edma1 3 0 FSL_EDMA_RX>, > > > > + <&edma1 4 0 FSL_EDMA_RX>, > > > > + <&edma1 5 0 FSL_EDMA_RX>; > > > > + /* tx* is output channel of asrc, it is rx channel for eDMA */ > > > > + dma-names =3D "rxa", "rxb", "rxc", "txa", "txb", "txc"; > > > > + fsl,asrc-rate =3D <8000>; > > > > + fsl,asrc-width =3D <16>; > > > > + fsl,asrc-clk-map =3D <1>; > > > > + power-domains =3D <&pd IMX_SC_R_ASRC_1>; > > > > + status =3D "disabled"; > > > > + }; > > > > + > > > > + sai4: sai@59820000 { > > > > + compatible =3D "fsl,imx8qm-sai"; > > > > + reg =3D <0x59820000 0x10000>; > > > > + interrupts =3D ; > > > > + clocks =3D <&sai4_lpcg 1>, > > > > + <&clk_dummy>, > > > > + <&sai4_lpcg 0>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>; > > > > + clock-names =3D "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > > > > + dmas =3D <&edma1 8 0 FSL_EDMA_RX>, <&edma1 9 0 0>; > > > > + dma-names =3D "rx", "tx"; > > > > + power-domains =3D <&pd IMX_SC_R_SAI_4>; > > > > + status =3D "disabled"; > > > > + }; > > > > + > > > > + sai5: sai@59830000 { > > > > + compatible =3D "fsl,imx8qm-sai"; > > > > + reg =3D <0x59830000 0x10000>; > > > > + interrupts =3D ; > > > > + clocks =3D <&sai5_lpcg 1>, > > > > + <&clk_dummy>, > > > > + <&sai5_lpcg 0>, > > > > + <&clk_dummy>, > > > > + <&clk_dummy>; > > > > + clock-names =3D "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > > > > + dmas =3D <&edma1 10 0 0>; > > > > + dma-names =3D "tx"; > > > > + power-domains =3D <&pd IMX_SC_R_SAI_5>; > > > > + status =3D "disabled"; > > > > + }; > > > > + > > > > + amix: amix@59840000 { > > > > + compatible =3D "fsl,imx8qm-audmix"; > > > > + reg =3D <0x59840000 0x10000>; > > > > + clocks =3D <&amix_lpcg 0>; > > > > + clock-names =3D "ipg"; > > > > + power-domains =3D <&pd IMX_SC_R_AMIX>; > > > > + dais =3D <&sai4>, <&sai5>; > > > > + status =3D "disabled"; > > > > + }; > > > > + > > > > + mqs: mqs@59850000 { > > > > + compatible =3D "fsl,imx8qm-mqs"; > > > > + reg =3D <0x59850000 0x10000>; > > > > + clocks =3D <&mqs0_lpcg 0>, > > > > + <&mqs0_lpcg 1>; > > > > + clock-names =3D "mclk", "core"; > > > > + power-domains =3D <&pd IMX_SC_R_MQS_0>; > > > > + status =3D "disabled"; > > > > + }; > > > > + > > > > + asrc0_lpcg: clock-controller@59400000 { > > > = > > > Please insert he lpcg nodes according to their address. > > > = > > > > + compatible =3D "fsl,imx8qxp-lpcg"; > > > > + reg =3D <0x59400000 0x10000>; > > > > + #clock-cells =3D <1>; > > > > + clocks =3D <&audio_ipg_clk>; > > > > + clock-indices =3D ; > > > > + clock-output-names =3D "asrc0_lpcg_ipg_clk"; > > > > + power-domains =3D <&pd IMX_SC_R_ASRC_0>; > > > > + }; > > > > + > > > > + esai0_lpcg: clock-controller@59410000 { > > > > + compatible =3D "fsl,imx8qxp-lpcg"; > > > > + reg =3D <0x59410000 0x10000>; > > > > + #clock-cells =3D <1>; > > > > + clocks =3D <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, > > > > + <&audio_ipg_clk>; > > > > + clock-indices =3D , ; > > > > + clock-output-names =3D "esai0_lpcg_extal_clk", > > > > + "esai0_lpcg_ipg_clk"; > > > > + power-domains =3D <&pd IMX_SC_R_ESAI_0>; > > > > + }; > > > > + > > > > + spdif0_lpcg: clock-controller@59420000 { > > > > + compatible =3D "fsl,imx8qxp-lpcg"; > > > > + reg =3D <0x59420000 0x10000>; > > > > + #clock-cells =3D <1>; > > > > + clocks =3D <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>, > > > > + <&audio_ipg_clk>; > > > > + clock-indices =3D , ; > > > > + clock-output-names =3D "spdif0_lpcg_tx_clk", > > > > + "spdif0_lpcg_gclkw"; > > > > + power-domains =3D <&pd IMX_SC_R_SPDIF_0>; > > > > + }; > > > > + > > > > + spdif1_lpcg: clock-controller@59430000 { > > > = > > > That's imx8qm only as well, no? > > > = > > > Thanks and best regards, > > > Alexander > > > = > > > > + compatible =3D "fsl,imx8qxp-lpcg"; > > > > + reg =3D <0x59430000 0x10000>; > > > > + #clock-cells =3D <1>; > > > > + clocks =3D <&acm IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL>, > > > > + <&audio_ipg_clk>; > > > > + clock-indices =3D , ; > > > > + clock-output-names =3D "spdif1_lpcg_tx_clk", > > > > + "spdif1_lpcg_gclkw"; > > > > + power-domains =3D <&pd IMX_SC_R_SPDIF_1>; > > > > + status =3D "disabled"; > > > > + }; > > > > + > > > > + asrc1_lpcg: clock-controller@59c00000 { > > > > + compatible =3D "fsl,imx8qxp-lpcg"; > > > > + reg =3D <0x59c00000 0x10000>; > > > > + #clock-cells =3D <1>; > > > > + clocks =3D <&audio_ipg_clk>; > > > > + clock-indices =3D ; > > > > + clock-output-names =3D "asrc1_lpcg_ipg_clk"; > > > > + power-domains =3D <&pd IMX_SC_R_ASRC_1>; > > > > + }; > > > > + > > > > + sai4_lpcg: clock-controller@59c20000 { > > > > + compatible =3D "fsl,imx8qxp-lpcg"; > > > > + reg =3D <0x59c20000 0x10000>; > > > > + #clock-cells =3D <1>; > > > > + clocks =3D <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, > > > > + <&audio_ipg_clk>; > > > > + clock-indices =3D , ; > > > > + clock-output-names =3D "sai4_lpcg_mclk", > > > > + "sai4_lpcg_ipg_clk"; > > > > + power-domains =3D <&pd IMX_SC_R_SAI_4>; > > > > + }; > > > > + > > > > + sai5_lpcg: clock-controller@59c30000 { > > > > + compatible =3D "fsl,imx8qxp-lpcg"; > > > > + reg =3D <0x59c30000 0x10000>; > > > > + #clock-cells =3D <1>; > > > > + clocks =3D <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, > > > > + <&audio_ipg_clk>; > > > > + clock-indices =3D , ; > > > > + clock-output-names =3D "sai5_lpcg_mclk", > > > > + "sai5_lpcg_ipg_clk"; > > > > + power-domains =3D <&pd IMX_SC_R_SAI_5>; > > > > + }; > > > > + > > > > + amix_lpcg: clock-controller@59c40000 { > > > > + compatible =3D "fsl,imx8qxp-lpcg"; > > > > + reg =3D <0x59c40000 0x10000>; > > > > + #clock-cells =3D <1>; > > > > + clocks =3D <&audio_ipg_clk>; > > > > + clock-indices =3D ; > > > > + clock-output-names =3D "amix_lpcg_ipg_clk"; > > > > + power-domains =3D <&pd IMX_SC_R_AMIX>; > > > > + }; > > > > + > > > > + mqs0_lpcg: clock-controller@59c50000 { > > > > + compatible =3D "fsl,imx8qxp-lpcg"; > > > > + reg =3D <0x59c50000 0x10000>; > > > > + #clock-cells =3D <1>; > > > > + clocks =3D <&acm IMX_ADMA_ACM_MQS_TX_CLK_SEL>, > > > > + <&audio_ipg_clk>; > > > > + clock-indices =3D , ; > > > > + clock-output-names =3D "mqs0_lpcg_mclk", > > > > + "mqs0_lpcg_ipg_clk"; > > > > + power-domains =3D <&pd IMX_SC_R_MQS_0>; > > > > + }; > > > > }; > > > > = > > > > = > > > = > > > = > > = > > = > = > = > -- = > TQ-Systems GmbH | M=FChlstra=DFe 2, Gut Delling | 82229 Seefeld, Germany > Amtsgericht M=FCnchen, HRB 105018 > Gesch=E4ftsf=FChrer: Detlef Schneider, R=FCdiger Stahl, Stefan Schneider > http://www.tq-group.com/ > = > = _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel