Re: [PATCH 3/3] dt-bindings: remoteproc: Add Arm remoteproc

Sudeep Holla
2024-03-14T15:19:39Z

On Thu, Mar 14, 2024 at 01:49:28PM +0000, Abdellatif El Khlifi wrote:
> Hi Robin,
>
> > > + firmware-name:
> > > + description: |
> > > + Default name of the firmware to load to the remote processor.
> >
> > So... is loading the firmware image achieved by somehow bitbanging it
> > through the one reset register, maybe? I find it hard to believe this is a
> > complete and functional binding.
> >
> > Frankly at the moment I'd be inclined to say it isn't even a remoteproc
> > binding (or driver) at all, it's a reset controller. Bindings are a contract
> > for describing the hardware, not the current state of Linux driver support -
> > if this thing still needs mailboxes, shared memory, a reset vector register,
> > or whatever else to actually be useful, those should be in the binding from
> > day 1 so that a) people can write and deploy correct DTs now, such that
> > functionality becomes available on their systems as soon as driver support
> > catches up, and b) the community has any hope of being able to review
> > whether the binding is appropriately designed and specified for the purpose
> > it intends to serve.
>
> This is an initial patchset for allowing to turn on and off the remote processor.
> The FW is already loaded before the Corstone-1000 SoC is powered on and this
> is done through the FPGA board bootloader in case of the FPGA target.
> Or by the Corstone-1000 FVP model (emulator).
>

If this driver does the loading of the firmware, it will get reloaded. Do
you need any issues there ? The correctness matters here in the upstream
driver, it may not be optimised for you usecase now, but that is fine IMO.

> The plan for the driver is as follows:
>
> Step 1: provide a foundation driver capable of turning the core on/off
> Step 2: provide mailbox support for comms
> Step 3: provide FW reload capability
>
> Steps 2 & 3 are waiting for a HW update so the Cortex-A35 (running Linux) can
> share memory with the remote core.
>

Honestly, I would prefer to know the overall design before pushing any partial
solution. If you know the final complete solution, present the same with
the complete device tree binding for better understanding and review.

> So, when memory sharing becomes available in the FPGA and FVP the
> DT binding will be upgraded with:
>
> - mboxes property specifying the RX/TX mailboxes (based on MHU v2)
> - memory-region property describing the virtio vrings
>

Looks like you have the information now, please define the complete
bindings now.

> Currently the mailbox controller does exist in the HW but is not
> usable via virtio (no memory sharing available).
>

That is fine, if the plan is to use them, then include them in the design
of your DT bindings.

> Do you recommend I add the mboxes property even currently we can't do the comms ?
>

Yes for sure IMO.

> > For instance right now it seems somewhat tenuous to describe two consecutive
> > 32-bit registers as separate "reg" entries, but *maybe* it's OK if that's
> > all there ever is. However if it's actually going to end up needing several
> > more additional MMIO and/or memory regions for other functionality, then
> > describing each register and location individually is liable to get
> > unmanageable really fast, and a higher-level functional grouping (e.g. these
> > reset-related registers together as a single 8-byte region) would likely be
> > a better design.
>

I completely agree with the above and this is what I was meant(I must admit
didn't put it forward with above clarity).

> Currently the HW provides only 2 registers to control the remote processors:
>
> The reset control and status registers.
>

Agreed, but it is part of a bigger block with other functionality in place.
MFD/syscon might be better way to use these registers. You never know in
future you might want to use another set of 2-4 registers with a different
functionality in another driver.

> It makes sense to me to use a mapped region of 8 bytes for both registers rather
> than individual registers (since they are consecutive).

Not exactly. Are you sure, Linux will not have to use another other registers
in that block ? Will you keep creating such (random if I may call it so)
bindings for a smaller sets of register under "Host Base System Control
registers".

I would see if it makes sense to put together a single binding for
this "Host Base System Control" register(not sure what exactly that means).
Use MFD/regmap you access parts of this block. The remoteproc driver can
then be semi-generic(meaning applicable to group of similar platforms)
based on the platform compatible and use this regmap to provide the
functionality needed.

--
Regards,
Sudeep