[PATCH v2 3/5] arm64: dts: corstone1000: Add MHU nodes used by the External System

Abdellatif El Khlifi
2024-08-22T17:13:22Z

Add normal world mhu0_hes0 and mhu0_es0h nodes

In Corstone-1000 IoT Reference Design Platform, communication between the
host (Cortex-A35) running in normal world (EL0 and EL1) and the external
system (Cortex-M3) is done with MHU0.

MHU0 is a bidirectional communication channel described in the device tree
through mhu0_hes0 and mhu0_es0h.

Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
---
arch/arm64/boot/dts/arm/corstone1000.dtsi | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi
index bb9b96fb5314..01c65195ca53 100644
--- a/arch/arm64/boot/dts/arm/corstone1000.dtsi
+++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
- * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022, 2024 Arm Limited. All rights reserved.
* Copyright (c) 2022, Linaro Limited. All rights reserved.
*
*/
@@ -134,6 +134,26 @@ uart1: serial@1a520000 {
clock-names = "uartclk", "apb_pclk";
};

+ mhu0_hes0: mhu@1b000000 {
+ compatible = "arm,mhuv2-tx","arm,primecell";
+ reg = <0x1b000000 0x1000>;
+ clocks = <&refclk100mhz>;
+ clock-names = "apb_pclk";
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ arm,mhuv2-protocols = <0 1>;
+ };
+
+ mhu0_es0h: mhu@1b010000 {
+ compatible = "arm,mhuv2-rx","arm,primecell";
+ reg = <0x1b010000 0x1000>;
+ clocks = <&refclk100mhz>;
+ clock-names = "apb_pclk";
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ arm,mhuv2-protocols = <0 1>;
+ };
+
mhu_hse1: mailbox@1b820000 {
compatible = "arm,mhuv2-tx", "arm,primecell";
reg = <0x1b820000 0x1000>;
--
2.25.1