From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4F8E6C54E66 for ; Fri, 15 Mar 2024 05:20:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:CC:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=TVbP9Gsav4Aq8X57yhlPstsoUXEjbhbdH0cA++TO6Ck=; b=eQvZdqN7Nd1XT/ 2Y9LgQ8aaAA6ISQ6GIivztF5bAGNha7ImDIkM4UEfjpGrscV2C/QA12VH/PzkpVFgLHkcXt2bDzHN PkohyQ00WnsU3+hr+xCQXOQdOJDMWYoZpJt6Ukb/0r2hvROXZ7obcieLgQ/6VuhrCWUCxJU7X3nNg 5PgyVApBHJFoqnVVQseRFnzSk6v0F0aepxs5YeOMa6dCNBqd2ma645T88YtiAnheqnIvehpOrnxDs woMOKGciPq5vDMZu+yjtGR8Cx0MpNw/LluRQV6bBFffvCPWFkAthgNPA/VhdPjvKXdBuVmfzBTAAp LVtIKT1S7TSJykS2sx7Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rkzzc-0000000GifA-0Qxf; Fri, 15 Mar 2024 05:20:32 +0000 Received: from mail-mw2nam12on20600.outbound.protection.outlook.com ([2a01:111:f403:200a::600] helo=NAM12-MW2-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rkzzY-0000000GieA-3H5x for linux-arm-kernel@lists.infradead.org; Fri, 15 Mar 2024 05:20:30 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=QRFBeeQ6j5p/wp1CCxfdpeL9JvjpPwoONp3fpdW7yHj2blBGx8kjDVEl3zFSxW4Pg5QnDTmu/ZA+TqL+9NDIoVkxarmsUyxOmxL4qafCzxbV38SmJ9lt3/Mtl7xaEOgGFcvCGrVM/Fb5TV7FNbR60GzlQxI45V5J2oJ0MBSypfEBpwxAvRmIoX4qdHP1UMl1k4lIfA5a/xeUd9C+H8MP0plBTHBkwiODaFodyELuUFz663xdL9Y/+Sx8lIS4dPgTrlFe2EnOfjwGw3k1VY+J6xA33nJAJo3eKUDnj4JGxwK7URR8C2QRd6fQ+Ez4JXcYrCDkcJ7VaWwylF83L7yONA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Bq1rD2iMlRvVpv1GKapRUKu8XwJRpMUDE/3NtCdLHDY=; b=EWXLwkvmOg8Gy7g1uQwitI2VK78GuF/F1XpMtlz/u+GfZgdLyplcBQhgA52i9tVJiLBaro37KOrNtwDYnVJrd5kdY2WCALKRKH45s0GXL1Vg9YUtxdr/80cSCndBWgM3hdexerbBEFFi1BAZFg+7DxU9VKfwnfpdOonV91YTPjxs93mucHBXH9a+08m6B+BNVaKuzlwjJOkPd1MGLSzHs37M+nfdTiMRK5RyGtF9nfPo9oBaFPjhG1bb6EwLEo00Va3/qWOmdnyIq8O7CecyB2RePrR930ERzIwZYMkCwka+D7LqhfbcCS/q7KFKGiYe1Pzgl6/97158i5wZs1KZZA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Bq1rD2iMlRvVpv1GKapRUKu8XwJRpMUDE/3NtCdLHDY=; b=Qxi8c66+rVMpMegOL2IlS2iKujXDCXziZQOlJ+d+9/PRumlww04XImEvwSfWtSJvZGMoqDPGDfxTuPegT1HCRqmfqTOaW64VrPMv9Ma0r/8MRaeHYdSvyTMB9SrbAVBicAumGLLolxLTk5ECx4xISD7FAaqzj0HqfpaE8DhnN5jxD7ehzvpxRwAF7hpI9AkVCkIogbXNQqkXkI+qi8WfdWXejwhG6f20+oeQjAMTc2uLzgKZtR7Mk5NCytQT3RhU+trFBrVMEHKP7YCMua/riLAtlQVQAjyqvq5J3S5NLyCt59Ljbau5LiTfahU8UICAGuLf7FObXOY/XEYazvPFAg== Received: from MW4PR04CA0161.namprd04.prod.outlook.com (2603:10b6:303:85::16) by LV8PR12MB9261.namprd12.prod.outlook.com (2603:10b6:408:1ed::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7386.22; Fri, 15 Mar 2024 05:20:18 +0000 Received: from MWH0EPF000A672E.namprd04.prod.outlook.com (2603:10b6:303:85:cafe::fa) by MW4PR04CA0161.outlook.office365.com (2603:10b6:303:85::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7386.20 via Frontend Transport; Fri, 15 Mar 2024 05:20:17 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by MWH0EPF000A672E.mail.protection.outlook.com (10.167.249.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7386.12 via Frontend Transport; Fri, 15 Mar 2024 05:20:17 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Thu, 14 Mar 2024 22:20:05 -0700 Received: from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 14 Mar 2024 22:20:04 -0700 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12 via Frontend Transport; Thu, 14 Mar 2024 22:20:02 -0700 Date: Thu, 14 Mar 2024 22:20:00 -0700 From: Nicolin Chen To: Michael Shavit , Jason Gunthorpe CC: , Joerg Roedel , , Robin Murphy , Will Deacon , Eric Auger , Jean-Philippe Brucker , Moritz Fischer , , Shameerali Kolothum Thodi Subject: Re: [PATCH v5 04/27] iommu/arm-smmu-v3: Add an ops indirection to the STE code Message-ID: References: <0-v5-9a37e0c884ce+31e3-smmuv3_newapi_p2_jgg@nvidia.com> <4-v5-9a37e0c884ce+31e3-smmuv3_newapi_p2_jgg@nvidia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A672E:EE_|LV8PR12MB9261:EE_ X-MS-Office365-Filtering-Correlation-Id: b1f0f7f6-897e-4411-e0ae-08dc44af9a40 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: RXaZhCuh/XrnxPLy3FBSDCklu/eTMPBoSj4XeEM2GYqw0bsnajSV2jMXOWY2rsd6wMgnpRrJ5GvZD/OUIabgdOa5FL7IaqEXUnlJzDAaOc/+/FmQSJXV0P7chJUpW+K1sttyEH8ZB6EnS6H2nzHnP4Uy4BSyYWamLcvAOGQCPcABbZsX7nMnS0oEbg8hTc1hrM7oG2EQMeJQXbjmZfcws6WdWLWLW/pVdo2Xm32cMjn8qpEaNteDNBftSKgxVyZyf7t0M11WE+Gv/7EGeY6E0goejCCnGoeIKHzUj6Xfi3A7CnbBgkqn0xLZugEmkHRft+HBOIG/pYDCj58apepSE0kwKtR7CJwlG11GOco5HXh6m1/NdrbHBGuspgJ4NGtqgapTwhNYuTt6e00rdRFV/FCheGOVcgspoig6kqXlZehgbKchl2TgozmvGV96jKhRFDFjMNhXzHz1wLCOhhfbo/+wS15gaHm5QcP9Z1s1Casfcv0JEu5Kd59GKRJmdpsEhe/xARjL1DbXPq0Yj2QV/oQ+gnSblLj+295R6E6CvFOPRcxX5d5Aeqgyb0BDjr/F+dGozzeF4vtJ9Yx9CHfVSmuAZ3ExmrwoFZqJGpb8XMSBXipxR26pBNB/+IT819aTe42pok7vSk6tD4stFL5XurSuBWH2zHKhZm/W/3eFs903flhlXN1Sdqlfdy6AePNGGd4JaG+w3faAW0TV3R3p8WS5IlqbIncDhP96oSGeVWKjXyoJeTcS/E2ZZaIC0uan X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(36860700004)(1800799015)(7416005)(82310400014)(376005);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Mar 2024 05:20:17.6270 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b1f0f7f6-897e-4411-e0ae-08dc44af9a40 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A672E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9261 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240314_222029_001912_89E2135C X-CRM114-Status: GOOD ( 23.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Mar 14, 2024 at 09:23:00PM -0700, Nicolin Chen wrote: > Hi Michael/Jason, > > On Mon, Mar 04, 2024 at 07:43:52PM -0400, Jason Gunthorpe wrote: > > Prepare to put the CD code into the same mechanism. Add an ops indirection > > around all the STE specific code and make the worker functions independent > > of the entry content being processed. > > > > get_used and sync ops are provided to hook the correct code. > > > > Signed-off-by: Michael Shavit > > Signed-off-by: Jason Gunthorpe With the following trivial comments being sent previously, I've also retested this version with SVA cases covering two different S1DSS configurations. This seems to be the only patch not tagged with Tested-by. So, Tested-by: Nicolin Chen Thanks Nicolin > > --- > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 172 ++++++++++++-------- > > 1 file changed, 104 insertions(+), 68 deletions(-) > > > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > index c60b067c1f553e..b7f947e36f596f 100644 > > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > @@ -48,8 +48,20 @@ enum arm_smmu_msi_index { > > ARM_SMMU_MAX_MSIS, > > }; > > > > -static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, > > - ioasid_t sid); > > +struct arm_smmu_entry_writer_ops; > > +struct arm_smmu_entry_writer { > > + const struct arm_smmu_entry_writer_ops *ops; > > + struct arm_smmu_master *master; > > +}; > > + > > +struct arm_smmu_entry_writer_ops { > > + unsigned int num_entry_qwords; > > I vaguely remember some related discussion, yet can't find it > out. So sorry for questioning this, if it's already discussed. > Aren't CD and STE having the same num_entry_qwords in terms of > their values? Feels like we can just use NUM_ENTRY_QWORDS? > > > + __le64 v_bit; > > + void (*get_used)(const __le64 *entry, __le64 *used); > > + void (*sync)(struct arm_smmu_entry_writer *writer); > > +}; > > + > > +#define NUM_ENTRY_QWORDS (sizeof(struct arm_smmu_ste) / sizeof(u64)) > > And this seems to be just a fixed "8"? Since both are defined > straightforwardly: > > struct arm_smmu_ste { > __le64 data[8]; > }; > ... > struct arm_smmu_cd { > __le64 data[8]; > }; > > Might be a bit nitpicking, yet maybe the other way around? > > #define NUM_ENTRY_QWORDS 8 > ... > struct arm_smmu_ste { > __le64 data[NUM_ENTRY_QWORDS]; > }; > ... > struct arm_smmu_cd { > __le64 data[NUM_ENTRY_QWORDS]; > }; > > Thanks > Nicolin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel