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Received: from shell.armlinux.org.uk ([fd8f:7570:feb6:1:5054:ff:fe00:4ec]:57550) by pandora.armlinux.org.uk with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1rnKQP-0007jl-0f; Thu, 21 Mar 2024 15:33:49 +0000 Received: from linux by shell.armlinux.org.uk with local (Exim 4.94.2) (envelope-from ) id 1rnKQJ-0003kc-MI; Thu, 21 Mar 2024 15:33:43 +0000 Date: Thu, 21 Mar 2024 15:33:43 +0000 From: "Russell King (Oracle)" To: David Laight Cc: Ard Biesheuvel , 'Jiangfeng Xiao' , "arnd@arndb.de" , "keescook@chromium.org" , "haibo.li@mediatek.com" , "angelogioacchino.delregno@collabora.com" , "amergnat@baylibre.com" , "akpm@linux-foundation.org" , "dave.hansen@linux.intel.com" , "douzhaolei@huawei.com" , "gustavoars@kernel.org" , "jpoimboe@kernel.org" , "kepler.chenxin@huawei.com" , "kirill.shutemov@linux.intel.com" , "linux-hardening@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-mm@kvack.org" , "linux-arm-kernel@lists.infradead.org" , "nixiaoming@huawei.com" , "peterz@infradead.org" , "wangbing6@huawei.com" , "wangfangpeng1@huawei.com" , "jannh@google.com" , "willy@infradead.org" Subject: Re: [PATCH v2] ARM: unwind: improve unwinders for noreturn case Message-ID: References: <0fd55e156195440bb1d815dd8300894b@AcuMS.aculab.com> <9d6057b110034c04b6b590522c8c69cc@AcuMS.aculab.com> <401453a216644af98d577f51c12d292b@AcuMS.aculab.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <401453a216644af98d577f51c12d292b@AcuMS.aculab.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240321_083416_784636_1CAF1C74 X-CRM114-Status: GOOD ( 29.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Mar 21, 2024 at 03:20:57PM +0000, David Laight wrote: > From: Russell King > > Sent: 21 March 2024 14:56 > > > > On Thu, Mar 21, 2024 at 02:37:28PM +0000, David Laight wrote: > > > From: Russell King > > > > Sent: 21 March 2024 13:08 > > > > > > > > On Thu, Mar 21, 2024 at 12:57:07PM +0000, David Laight wrote: > > > > > From: Russell King > > > > > > Sent: 21 March 2024 12:23 > > > > > ... > > > > > > > That might mean you can get the BL in the middle of a function > > > > > > > but where the following instruction is for the 'no stack frame' > > > > > > > side of the branch. > > > > > > > That is very likely to break any stack offset calculations. > > > > > > > > > > > > No it can't. At any one point in the function, the stack has to be in > > > > > > a well defined state, so that access to local variables can work, and > > > > > > also the stack can be correctly unwound. If there exists a point in > > > > > > the function body which can be reached where the stack could be in two > > > > > > different states, then the stack can't be restored to the parent > > > > > > context. > > > > > > > > > > Actually you can get there with a function that has a lot of args. > > > > > So you can have: > > > > > if (...) { > > > > > push x > > > > > bl func > > > > > add %sp, #8 > > > > > } > > > > > code; > > > > > which is fine. > > > > > > > > No you can't.... and that isn't even Arm code. Arm doesn't use %sp. > > > > Moreover, that "bl" will stomp over the link register, meaning this > > > > function can not return. > > > > ... > > > > Don't show me Arm64 assembly when we're discussing Arm32. > > Oops - I'd assumed no one did 32bit :-) > In any case it is much the same, see https://godbolt.org/z/7dcbKrs76 > > f4: > push {r3, lr} > subs r3, r0, #0 > ble .L2 > mov r2, r3 > mov r1, r3 > bl f > .L2: > pop {r3, pc} > > f5: > subs r3, r0, #0 > ble .L6 > push {lr} > sub sp, sp, #12 > mov r2, r3 > mov r1, r3 > str r3, [sp] > bl f > .L6: > bx lr > > That is with -mno-sched-prolog but with 5+ args they spill to stack > and the %sp change is pulled into the conditional. > > It does look like %lr is being saved (and for arm64 I think). I see nothing that contradicts anything I've said in your example output. You have been previously refering to a "bl" in the prologue, which is what I thought you were going to give an example of. There is no "bl" in the prologue of f5, the "ble" instruction is a normal branch for less-than-or-equal. It's b + le not bl + e. At .L6, there will be a difference in stack, but as f() is declared as no-return, anything that comes after it is utterly irrelevant as control is not expected to reach any following instruction via that path. If it _were_ to, then in the example you give above, because "lr" points at the bx lr instruction, the result would be to endlessly spin executing bx lr instructions. -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last! _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel