From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 61DF7CD128A for ; Wed, 3 Apr 2024 10:02:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=d7f0sLU1DqhCZhbFa7cEtVFf+1EVhQaLIa+/F0cUrfI=; b=yyEaRw8fJVRRL4 lLJQhICeR48VO1JqSxvunPxjTSASkWrFZ3/1+kiPvN3g1nThM3+5ByRU/P4CBXuauKcCcVDfHL7H4 z4qCA7Kd967kCIWUqYeXU7qc0/CbloQUeF02BOjZLIpRYsfTJTtW1VZmlB+vSSUDMcxZtorkDZvWs XseRWZDB0vpyxL7qpw1m30PRDbXvEJh4N7Hwb5JTvwlOzWlpyYCwFWvCT0//rPCw779c7KMUsMDIp 0Xx4HUA1fMsyVy8lQfV0kDNQ24D7th7m1HN197kpFY0oecatiidmZyBhQeTDF9U3Bd7xgRXItmjfN DEtuzRhDhmLbj+AEszCg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrxRO-0000000FM1I-1XJE; Wed, 03 Apr 2024 10:01:58 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrxRL-0000000FLzN-0EoW for linux-arm-kernel@lists.infradead.org; Wed, 03 Apr 2024 10:01:56 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C44C2FEC; Wed, 3 Apr 2024 03:02:25 -0700 (PDT) Received: from FVFF77S0Q05N (unknown [10.57.16.212]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B3FF53F64C; Wed, 3 Apr 2024 03:01:52 -0700 (PDT) Date: Wed, 3 Apr 2024 11:01:49 +0100 From: Mark Rutland To: Seongsu Park Cc: will@kernel.org, catalin.marinas@arm.com, ardb@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Leem ChaeHoon , Gyeonggeon Choi , Soomin Cho , DaeRo Lee , kmasta Subject: Re: [PATCH v2] arm64: Fix double TCR_T0SZ_OFFSET shift Message-ID: References: <20240403024236.193428-1-sgsu.park@samsung.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240403024236.193428-1-sgsu.park@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240403_030155_224971_3EF01F2D X-CRM114-Status: GOOD ( 17.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Apr 03, 2024 at 11:42:36AM +0900, Seongsu Park wrote: > We have already shifted the value of t0sz in TCR_T0SZ by TCR_T0SZ_OFFSET. > So, the TCR_T0SZ_OFFSET shift here should be removed. Can we please write a better commit message? This doesn't explain: * Where we have already shifted the value of t0sz, nor why it makes sense to do that there. * That the value of TCR_T0SZ_OFFSET is 0, and hence shifting this repeatedly is beningn, and this patch is a cleanup rather than a fix. Mark. > Co-developed-by: Leem ChaeHoon > Signed-off-by: Leem ChaeHoon > Co-developed-by: Gyeonggeon Choi > Signed-off-by: Gyeonggeon Choi > Co-developed-by: Soomin Cho > Signed-off-by: Soomin Cho > Co-developed-by: DaeRo Lee > Signed-off-by: DaeRo Lee > Co-developed-by: kmasta > Signed-off-by: kmasta > Signed-off-by: Seongsu Park > --- > > Changes in v2: > - Condition is updated > > --- > arch/arm64/include/asm/mmu_context.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h > index c768d16b81a4..bd19f4c758b7 100644 > --- a/arch/arm64/include/asm/mmu_context.h > +++ b/arch/arm64/include/asm/mmu_context.h > @@ -72,11 +72,11 @@ static inline void __cpu_set_tcr_t0sz(unsigned long t0sz) > { > unsigned long tcr = read_sysreg(tcr_el1); > > - if ((tcr & TCR_T0SZ_MASK) >> TCR_T0SZ_OFFSET == t0sz) > + if ((tcr & TCR_T0SZ_MASK) == t0sz) > return; > > tcr &= ~TCR_T0SZ_MASK; > - tcr |= t0sz << TCR_T0SZ_OFFSET; > + tcr |= t0sz; > write_sysreg(tcr, tcr_el1); > isb(); > } > -- > 2.34.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel