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Tue, 16 Apr 2024 13:43:10 -0700 (PDT) Received: from ghost ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id lg7-20020a170902fb8700b001e259719a5fsm10208534plb.103.2024.04.16.13.43.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Apr 2024 13:43:09 -0700 (PDT) Date: Tue, 16 Apr 2024 13:43:06 -0700 From: Charlie Jenkins To: Conor Dooley Cc: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Evan Green , =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= , Jonathan Corbet , Shuah Khan , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH v2 02/17] dt-bindings: riscv: Add xtheadvector ISA extension description Message-ID: References: <20240415-dev-charlie-support_thead_vector_6_9-v2-0-c7d68c603268@rivosinc.com> <20240415-dev-charlie-support_thead_vector_6_9-v2-2-c7d68c603268@rivosinc.com> <20240416-underwire-bright-b2ab0fa991ec@spud> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240416-underwire-bright-b2ab0fa991ec@spud> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240416_134314_935737_87345092 X-CRM114-Status: GOOD ( 22.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Apr 16, 2024 at 04:16:30PM +0100, Conor Dooley wrote: > On Mon, Apr 15, 2024 at 09:11:59PM -0700, Charlie Jenkins wrote: > > The xtheadvector ISA extension is described on the T-Head extension spec > > Github page [1] at commit 95358cb2cca9. > > > > Link: https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d3 > > 35e03d3134b14133f/xtheadvector.adoc [1] > > This should not be wrapped btw. > Otherwise, > Reviewed-by: Conor Dooley I don't believe it is wrapped? It appears wrapped in your response but it appears on lore correctly: https://lore.kernel.org/lkml/20240415-dev-charlie-support_thead_vector_6_9-v2-2-c7d68c603268@rivosinc.com/ - Charlie > > Thanks, > Conor. > > > > > Signed-off-by: Charlie Jenkins > > --- > > Documentation/devicetree/bindings/riscv/extensions.yaml | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > > index 468c646247aa..99d2a9e8c52d 100644 > > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > > @@ -477,6 +477,10 @@ properties: > > latency, as ratified in commit 56ed795 ("Update > > riscv-crypto-spec-vector.adoc") of riscv-crypto. > > > > + # vendor extensions, each extension sorted alphanumerically under the > > + # vendor they belong to. Vendors are sorted alphanumerically as well. > > + > > + # Andes > > - const: xandespmu > > description: > > The Andes Technology performance monitor extension for counter overflow > > @@ -484,5 +488,11 @@ properties: > > Registers in the AX45MP datasheet. > > https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf > > > > + # T-HEAD > > + - const: xtheadvector > > + description: > > + The T-HEAD specific 0.7.1 vector implementation as written in > > + https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc. > > + > > additionalProperties: true > > ... > > > > -- > > 2.44.0 > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel