From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A5837C04FF6 for ; Tue, 16 Apr 2024 20:40:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=U09A46yim92XTcuyCXF+022jja3vxrRgDohIucVy+xU=; b=OpGyGFxgNBOuDG ey/jrQVFnIPR93F6JpdqsBQELb/6jcHYLDPe80yj+e7ORf4MS7uwpBo7msDYsOmISGsRyfRpxTafT X2k4uLqEjIkavOkAuHV641uegMQG8UkusQ1S7WojsUyQuFzNHi1pwjcaNFojMtRRHmJdzNR58GdQw 50GiqfR8Xt4+rgi5CwISmC8kn/Y+b8quSLh3F4f2SCJedYre6RcgYUdi3tHSSJ39tYd1k/BvxpZSJ qS6f5Ci87cUc7MaUm5uOuQ488TCfEFgaPr0sHZhKd7AZCyFdHLp04qrsxYxbpEbeKTlro6R2BgJ5p GW9HI1fM0pB5PO5acmlg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rwpbb-0000000Dke6-1Coz; Tue, 16 Apr 2024 20:40:39 +0000 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rwpbR-0000000DkYh-2lNh for linux-arm-kernel@lists.infradead.org; Tue, 16 Apr 2024 20:40:35 +0000 Received: by mail-pj1-x1034.google.com with SMTP id 98e67ed59e1d1-2a564ca6f67so4057397a91.2 for ; Tue, 16 Apr 2024 13:40:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1713300028; x=1713904828; darn=lists.infradead.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=QVjtMTyKyhNTcN+UpxkEkTpYsqk+JWf4FRaAP28rhDY=; b=S9iEWKVzXALpBxjzQXrf+YMR8BTW1NkHXCSN5XL8hVRc1rVAndXMXBhEUhnmhA76MO /ngYqlWStOKi+fWhaUpyA9xV0uvsLd8i8QnB8CRdfxZbgjQjg5lOvhUOq4NC+gpT0DXd ZnGe8CALh+eSoukz0oDaWMljX3cNYWhsRAlJCwiTllNE+/7hGU1MycGuqY38lVqT0VBC 8OobtIX2SS0EBM4LFnnbilyD8NPh4BC5ZowhGKkMFNCUHDrCu9enVKEZur4C93SqHOVS EQpSIhJjRtPcj+TgD1bHGoLi7J8ILeDj8yWIfwboRTjCjl7EVqYAC0wcmbWas1wDv9Rh qFgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1713300028; x=1713904828; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=QVjtMTyKyhNTcN+UpxkEkTpYsqk+JWf4FRaAP28rhDY=; b=NhM3XYQSoNMUveBg0B0M9dxzyyUIPz1Rx/x+ryNSjutUqpskrjm2fJjFHGZqkvg9ev 6OZO+31cJh5KfSq/6DjPXmq9LhQcThmG/NaayQ84Ux3yA8q6Wge1WfCFH6OE1Y8fgt4I AYHjYRwoREChrwbEsGwglejgLmDDsA4CAI2HkC/n8rk5aqUvRffiodpsf/32rJvgz0xh n7bUH79D7cgZE7HyHCEM9L2yu0EGvKSAhXPkmuPTNSafD1jYQek6k/xgK5dDx2MRbd98 pc7qIdqmLNzCSzvvOL6hFjGMTaohrA9YTHWIMAAplC2383GpGem5gLMWGdKAogEOlMyG 8xgA== X-Forwarded-Encrypted: i=1; AJvYcCUbBIPWjvNM/MMZUHhSj9eK12hgxKJDNv5BQfVzOA8LacGvVTpY4Vi1U55LSNX/vTFhQ5te5v0f7rHm9zsP9Wg3mGKxFhA8CGx/z8fXY92S8w6BOPk= X-Gm-Message-State: AOJu0YyEK/8LAqvkAZ11NPNAMIWcurlC8DcgA3pd56ObD0XwC82ONHFc 6vc7QoFm9yIMD2sXVQh0Z8x14m95GjHzcd5vwMkkrfjsBmcFKOsT6VO9QbFFfws= X-Google-Smtp-Source: AGHT+IHM3uUWSKt1fI9qO1XxrOHXkeZZaIcR3NFlAXNG12q5BaEwGvMZBQDoAX4Ml6q5YxA9kVBZNQ== X-Received: by 2002:a17:90a:e648:b0:2a2:acf3:4108 with SMTP id ep8-20020a17090ae64800b002a2acf34108mr16278208pjb.0.1713300028470; Tue, 16 Apr 2024 13:40:28 -0700 (PDT) Received: from ghost ([50.145.13.30]) by smtp.gmail.com with ESMTPSA id j6-20020a17090aeb0600b002a574ab7f5esm12038pjz.53.2024.04.16.13.40.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 Apr 2024 13:40:28 -0700 (PDT) Date: Tue, 16 Apr 2024 13:40:25 -0700 From: Charlie Jenkins To: Conor Dooley Cc: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Evan Green , =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= , Jonathan Corbet , Shuah Khan , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH v2 01/17] riscv: cpufeature: Fix thead vector hwcap removal Message-ID: References: <20240415-dev-charlie-support_thead_vector_6_9-v2-0-c7d68c603268@rivosinc.com> <20240415-dev-charlie-support_thead_vector_6_9-v2-1-c7d68c603268@rivosinc.com> <20240416-swipe-flattered-7cdccc01f0fe@spud> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240416-swipe-flattered-7cdccc01f0fe@spud> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240416_134029_879850_07B5FD2B X-CRM114-Status: GOOD ( 32.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Apr 16, 2024 at 04:03:20PM +0100, Conor Dooley wrote: > On Mon, Apr 15, 2024 at 09:11:58PM -0700, Charlie Jenkins wrote: > > The riscv_cpuinfo struct that contains mvendorid and marchid is not > > populated until all harts are booted which happens after the DT parsing. > > Use the vendorid/archid values from the DT if available or assume all > > harts have the same values as the boot hart as a fallback. > > > > Fixes: d82f32202e0d ("RISC-V: Ignore V from the riscv,isa DT property on older T-Head CPUs") > > Signed-off-by: Charlie Jenkins > > --- > > arch/riscv/include/asm/sbi.h | 2 ++ > > arch/riscv/kernel/cpu.c | 36 ++++++++++++++++++++++++++++++++---- > > arch/riscv/kernel/cpufeature.c | 12 ++++++++++-- > > 3 files changed, 44 insertions(+), 6 deletions(-) > > > > diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h > > index 6e68f8dff76b..0fab508a65b3 100644 > > --- a/arch/riscv/include/asm/sbi.h > > +++ b/arch/riscv/include/asm/sbi.h > > @@ -370,6 +370,8 @@ static inline int sbi_remote_fence_i(const struct cpumask *cpu_mask) { return -1 > > static inline void sbi_init(void) {} > > #endif /* CONFIG_RISCV_SBI */ > > > > +unsigned long riscv_get_mvendorid(void); > > +unsigned long riscv_get_marchid(void); > > unsigned long riscv_cached_mvendorid(unsigned int cpu_id); > > unsigned long riscv_cached_marchid(unsigned int cpu_id); > > unsigned long riscv_cached_mimpid(unsigned int cpu_id); > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > > index d11d6320fb0d..8c8250b98752 100644 > > --- a/arch/riscv/kernel/cpu.c > > +++ b/arch/riscv/kernel/cpu.c > > @@ -139,6 +139,34 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid) > > return -1; > > } > > > > +unsigned long __init riscv_get_marchid(void) > > +{ > > + struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo); > > + > > +#if IS_ENABLED(CONFIG_RISCV_SBI) > > + ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid(); > > +#elif IS_ENABLED(CONFIG_RISCV_M_MODE) > > + ci->marchid = csr_read(CSR_MARCHID); > > +#else > > + ci->marchid = 0; > > +#endif > > + return ci->marchid; > > +} > > + > > +unsigned long __init riscv_get_mvendorid(void) > > +{ > > + struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo); > > + > > +#if IS_ENABLED(CONFIG_RISCV_SBI) > > + ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid(); > > +#elif IS_ENABLED(CONFIG_RISCV_M_MODE) > > + ci->mvendorid = csr_read(CSR_MVENDORID); > > +#else > > + ci->mvendorid = 0; > > +#endif > > + return ci->mvendorid; > > +} > > + > > DEFINE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); > > > > unsigned long riscv_cached_mvendorid(unsigned int cpu_id) > > @@ -170,12 +198,12 @@ static int riscv_cpuinfo_starting(unsigned int cpu) > > struct riscv_cpuinfo *ci = this_cpu_ptr(&riscv_cpuinfo); > > > > #if IS_ENABLED(CONFIG_RISCV_SBI) > > - ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid(); > > - ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid(); > > + ci->mvendorid = ci->mvendorid ? ci->mvendorid : sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid(); > > + ci->marchid = ci->marchid ? ci->marchid : sbi_spec_is_0_1() ? 0 : sbi_get_marchid(); > > Can we please not have double ternary stuff? This is awful to grok :( > Can you do > if (!ci->m*id) > sbi_spec_is_0_1() ? 0 : sbi_get_m*id(); > instead? I think that is much easier to understand. > Otherwise, > Reviewed-by: Conor Dooley Sure, thanks! - Charlie > > Cheers, > Conor. > > > ci->mimpid = sbi_spec_is_0_1() ? 0 : sbi_get_mimpid(); > > #elif IS_ENABLED(CONFIG_RISCV_M_MODE) > > - ci->mvendorid = csr_read(CSR_MVENDORID); > > - ci->marchid = csr_read(CSR_MARCHID); > > + ci->mvendorid = ci->mvendorid ? ci->mvendorid : csr_read(CSR_MVENDORID); > > + ci->marchid = ci->marchid ? ci->marchid : csr_read(CSR_MARCHID); > > ci->mimpid = csr_read(CSR_MIMPID); > > #else > > ci->mvendorid = 0; > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > > index 3ed2359eae35..c6e27b45e192 100644 > > --- a/arch/riscv/kernel/cpufeature.c > > +++ b/arch/riscv/kernel/cpufeature.c > > @@ -490,6 +490,8 @@ static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap) > > struct acpi_table_header *rhct; > > acpi_status status; > > unsigned int cpu; > > + u64 boot_vendorid; > > + u64 boot_archid; > > > > if (!acpi_disabled) { > > status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct); > > @@ -497,6 +499,13 @@ static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap) > > return; > > } > > > > + /* > > + * Naively assume that all harts have the same mvendorid/marchid as the > > + * boot hart. > > + */ > > + boot_vendorid = riscv_get_mvendorid(); > > + boot_archid = riscv_get_marchid(); > > + > > for_each_possible_cpu(cpu) { > > struct riscv_isainfo *isainfo = &hart_isa[cpu]; > > unsigned long this_hwcap = 0; > > @@ -544,8 +553,7 @@ static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap) > > * CPU cores with the ratified spec will contain non-zero > > * marchid. > > */ > > - if (acpi_disabled && riscv_cached_mvendorid(cpu) == THEAD_VENDOR_ID && > > - riscv_cached_marchid(cpu) == 0x0) { > > + if (acpi_disabled && boot_vendorid == THEAD_VENDOR_ID && boot_archid == 0x0) { > > this_hwcap &= ~isa2hwcap[RISCV_ISA_EXT_v]; > > clear_bit(RISCV_ISA_EXT_v, isainfo->isa); > > } > > > > -- > > 2.44.0 > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel