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Fri, 12 Apr 2024 10:34:31 -0700 (PDT) Received: from ghost ([2601:647:5700:6860:121b:da6b:94f1:304]) by smtp.gmail.com with ESMTPSA id fs6-20020a17090af28600b002a4e331cc69sm4732571pjb.20.2024.04.12.10.34.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Apr 2024 10:34:31 -0700 (PDT) Date: Fri, 12 Apr 2024 10:34:28 -0700 From: Charlie Jenkins To: Conor Dooley Cc: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Evan Green , =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= , Jonathan Corbet , Shuah Khan , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH 07/19] riscv: Optimize riscv_cpu_isa_extension_(un)likely() Message-ID: References: <20240411-dev-charlie-support_thead_vector_6_9-v1-0-4af9815ec746@rivosinc.com> <20240411-dev-charlie-support_thead_vector_6_9-v1-7-4af9815ec746@rivosinc.com> <20240412-aerosol-heritage-cec1eca172fb@wendy> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240412-aerosol-heritage-cec1eca172fb@wendy> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240412_103441_030923_3FC13531 X-CRM114-Status: GOOD ( 23.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Apr 12, 2024 at 11:40:38AM +0100, Conor Dooley wrote: > On Thu, Apr 11, 2024 at 09:11:13PM -0700, Charlie Jenkins wrote: > > When alternatives are disabled, riscv_cpu_isa_extension_(un)likely() > > checks if the current cpu supports the selected extension if not all > > cpus support the extension. It is sufficient to only check if the > > current cpu supports the extension. > > > > The alternatives code to handle if all cpus support an extension is > > factored out into a new function to support this. > > > > Signed-off-by: Charlie Jenkins > > --- > > > static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsigned long ext) > > { > > - if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_unlikely(ext)) > > - return true; > > + compiletime_assert(ext < RISCV_ISA_EXT_MAX, > > + "ext must be < RISCV_ISA_EXT_MAX"); > > > > - return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); > > + if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && __riscv_has_extension_unlikely_alternatives(ext)) > > + return true; > > + else > > + return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); > > } > > static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const unsigned long ext) > { > if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_likely(ext)) > return true; > > return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); > } > > This is the code as things stand. If alternatives are disabled, the if > statement becomes if (0 && foo) which will lead to the function call > getting constant folded away and all you end up with is the call to > __riscv_isa_extension_available(). Unless I am missing something, I don't > think this patch has any affect? Yeah I fumbled this one it appears. I got thrown off by the nested IS_ENABLED(CONFIG_RISCV_ALTERNATIVE). This patch eliminates the need for this and maybe can avoid avoid confusion in the future. - Charlie > > Thanks, > Conor. > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel