From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C373EC4345F for ; Mon, 15 Apr 2024 08:32:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=8YHjZulIUQnX3/mR92l/F7KHImjBqRY7LzMRVERjwDE=; b=hbuNZWmyquwj0G wQW2ykwr9puZiiAMlWVacy1ROL3mp4Ko9v1K+jP9T6bOEz9pTfkd++jzmHm7Byst3ENEZpB3Vn5pO HhkfaeFwR2vCokRMafSWK0W8RLmvy5lhbpHsQQeOxx+A7q6NYy+aY9loM9pxL7EpDVNm9M4MyLmx/ ky5wQOGI6KELhC4IGlCgAwd3hRKenDLjB9xyCiQhpVVSI0uwLS+c8YotPpWu8z/V+Pap56TzcN3Gw wLnaQb+YYWZQFe/XHhj+y+FNsU37R71WuH0bO8Xtc/WKp75l7H8qV7HuIhnNMPLsQmgrcJyFv4pfj tUWPyk80p9cLzoxBkRCQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rwHlC-00000007YHc-03Zt; Mon, 15 Apr 2024 08:32:18 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rwHl9-00000007YHB-1SMw for linux-arm-kernel@lists.infradead.org; Mon, 15 Apr 2024 08:32:16 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B85FE2F; Mon, 15 Apr 2024 01:32:42 -0700 (PDT) Received: from FVFF77S0Q05N (unknown [10.57.20.152]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 33BF43F64C; Mon, 15 Apr 2024 01:32:13 -0700 (PDT) Date: Mon, 15 Apr 2024 09:32:10 +0100 From: Mark Rutland To: Ard Biesheuvel Cc: linux-arm-kernel@lists.infradead.org, Ard Biesheuvel , Catalin Marinas , Will Deacon , Marc Zyngier Subject: Re: [PATCH 2/2] arm64/head: Disable MMU at EL2 before clearing HCR_EL2.E2H Message-ID: References: <20240415075412.2347624-4-ardb+git@google.com> <20240415075412.2347624-6-ardb+git@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240415075412.2347624-6-ardb+git@google.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240415_013215_453308_40F5A84F X-CRM114-Status: GOOD ( 23.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Apr 15, 2024 at 09:54:15AM +0200, Ard Biesheuvel wrote: > From: Ard Biesheuvel > > Even though the boot protocol stipulates otherwise, an exception has > been made for the EFI stub, and entering the core kernel with the MMU > enabled is permitted. This allows a substantial amount of cache > maintenance to be elided, wich is significant when fast boot times are > critical (e.g., for booting micro-VMs) > > Once the initial ID map has been populated, the MMU is disabled as part > of the logic sequence that puts all system registers into a known state. > Any code that needs to execute within the window where the MMU is off is > cleaned to the PoC explicitly, which includes all of HYP text when > entering at EL2. > > However, the current sequence of initializing the EL2 system registers > is not safe: HCR_EL2 is set to its nVHE initial state before SCTLR_EL2 > is reprogrammed, and this means that a VHE-to-nVHE switch may occur > while the MMU is enabled. This switch causes some system registers as > well as page table descriptors to be interpreted in a different way, > potentially resulting in spurious exceptions relating to MMU > translation. > > So disable the MMU explicitly first when entering in EL2 with the MMU > and caches enabled. > > Signed-off-by: Ard Biesheuvel Acked-by: Mark Rutland Mark. > --- > arch/arm64/kernel/head.S | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S > index b8bbd72cb194..cb68adcabe07 100644 > --- a/arch/arm64/kernel/head.S > +++ b/arch/arm64/kernel/head.S > @@ -289,6 +289,11 @@ SYM_INNER_LABEL(init_el2, SYM_L_LOCAL) > adr_l x1, __hyp_text_end > adr_l x2, dcache_clean_poc > blr x2 > + > + mov_q x0, INIT_SCTLR_EL2_MMU_OFF > + pre_disable_mmu_workaround > + msr sctlr_el2, x0 > + isb > 0: > mov_q x0, HCR_HOST_NVHE_FLAGS > > -- > 2.44.0.683.g7961c838ac-goog > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel