From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 123B4C4345F for ; Thu, 18 Apr 2024 10:41:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=XoiZG9GU4IhZ0wtRlhz90SQ/StViDh/O2UC8k0uzyKQ=; b=qflsbrHWSlZDyb 2VL6oBtCXUVhMGjTyUmsSIKDCa4NBbPxOsr+qUfKBuXZ4Gzi93mii4Bi+ykPnIT10kdm4A1H90chv 9+mRK5Tim5sRVn8nN2EkVyPC95M+l+Q5WEzTpvz0ExEcdybBt9BL7aVEQiH0dX50HkFSOOLotgu2J Kg1iGEnqozg0g97NtuHENfnGGaAwPkT2+plWaqApLtIXa7qv1+qV3VwSktk7j0GpMNc5oqJEr9Kkt //0Eryr8jMS9IYJ9K5atSK84GAgiZNO1IL+fV8otQFMjPUOsZaigBwVocmbf8DVyx0V4BGRVsu9Tw bjK9iB50T3UbjbRiKU6A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxPCH-00000001qYY-2tx1; Thu, 18 Apr 2024 10:40:53 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rxPCF-00000001qY1-0czW for linux-arm-kernel@lists.infradead.org; Thu, 18 Apr 2024 10:40:52 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A049D339; Thu, 18 Apr 2024 03:41:17 -0700 (PDT) Received: from FVFF77S0Q05N (unknown [10.57.19.64]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2A3AC3F64C; Thu, 18 Apr 2024 03:40:49 -0700 (PDT) Date: Thu, 18 Apr 2024 11:40:46 +0100 From: Mark Rutland To: Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org, Marc Zyngier Subject: Re: [bootwrapper PATCH 2/2] aarch64: Disable trapping into EL3 while accessing FEAT_FGT2 registers Message-ID: References: <20240404073726.947215-1-anshuman.khandual@arm.com> <20240404073726.947215-3-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240404073726.947215-3-anshuman.khandual@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240418_034051_251881_BF6F2950 X-CRM114-Status: GOOD ( 16.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Apr 04, 2024 at 01:07:26PM +0530, Anshuman Khandual wrote: > This disables trapping into EL3 while accessing Fine Grained Traps Enable 2 > (i.e FEAT_FGT2) registers such as HDFGRTR2_EL2, HDFGWTR2_EL2, HFGITR2_EL2, > HFGRTR2_EL2 and HFGWTR2_EL2 via setting SCR_EL3.FGTEN2. But first ensure > that FEAT_FGT2 feature is implemented looking into ID_AA64MMFR0_EL1. I think for clarity that should be: | aarch64: Enable access to FGT2 registers from EL2 and below | | FEAT_FGT2 adds a number of registers: HFGITR2_EL2, HFGRTR2_EL2, | HFGWTR_EL2, HDFGRTR2_EL2, and HDFGWTR2_EL2. Acceses to these from EL2 | trap to EL3 unless SCR_EL3.FGTEN2 is set. | | Enable access to the FGT2 registers when they are implemented. However, I note that those registers have fields that reset to UNKNOWN values when resets are taken to EL3. That means we must initialise those to sane values to avoid breaking existing EL2 code with unexpected traps. I know that we didn't do that for FGT, which really was a mistake. I reckon we should reset all of the FGT regsiters to sane values (i.e. existing features shouldn't trap, new features should trap). We'll also need to ensure that Trusted Firmware does likewise... Mark. > > Signed-off-by: Anshuman Khandual > --- > arch/aarch64/include/asm/cpu.h | 1 + > arch/aarch64/init.c | 3 +++ > 2 files changed, 4 insertions(+) > > diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h > index 124ef91..56f319a 100644 > --- a/arch/aarch64/include/asm/cpu.h > +++ b/arch/aarch64/include/asm/cpu.h > @@ -57,6 +57,7 @@ > #define SCR_EL3_EnTP2 BIT(41) > #define SCR_EL3_TCR2EN BIT(43) > #define SCR_EL3_PIEN BIT(45) > +#define SCR_EL3_FGTEN2 BIT(59) > > #define HCR_EL2_RES1 BIT(1) > > diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c > index 37cb45f..557266b 100644 > --- a/arch/aarch64/init.c > +++ b/arch/aarch64/init.c > @@ -68,6 +68,9 @@ void cpu_init_el3(void) > if (mrs_field(ID_AA64MMFR0_EL1, FGT)) > scr |= SCR_EL3_FGTEN; > > + if (mrs_field(ID_AA64MMFR0_EL1, FGT) >= 2) > + scr |= SCR_EL3_FGTEN2; > + > if (mrs_field(ID_AA64MMFR0_EL1, ECV) >= 2) > scr |= SCR_EL3_ECVEN; > > -- > 2.25.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel