From: Arnaldo Carvalho de Melo <acme@kernel.org>
To: Tanmay Jagdale <tanmay@marvell.com>
Cc: john.g.garry@oracle.com, will@kernel.org, james.clark@arm.com,
mike.leach@linaro.org, leo.yan@linux.dev, suzuki.poulose@arm.com,
peterz@infradead.org, mingo@redhat.com,
alexander.shishkin@linux.intel.com, jolsa@kernel.org,
irogers@google.com, adrian.hunter@intel.com,
linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
sgoutham@marvell.com, gcherian@marvell.com, lcherian@marvell.com
Subject: Re: [PATCH V2 0/2] Fix Coresight instruction synthesis logic
Date: Thu, 25 Apr 2024 15:54:09 -0300 [thread overview]
Message-ID: <Ziqm0QYfGbYjF6xh@x1> (raw)
In-Reply-To: <20240404180731.7006-1-tanmay@marvell.com>
On Thu, Apr 04, 2024 at 11:37:29PM +0530, Tanmay Jagdale wrote:
> When we use perf to catpure Coresight trace and generate instruction
> trace using 'perf script', we get the following output:
>
> # perf record -e cs_etm/@tmc_etr0/ -C 9 taskset -c 9 sleep 1
> # perf script --itrace=i1ns --ns -Fcomm,tid,pid,time,cpu,event,ip,sym,addr,symoff,flags,callindent
Applies cleanly, can some Coresight people review this and provide a
Reviewed-by?
Thanks!
- Arnaldo
⬢[acme@toolbox perf-tools-next]$ b4 am -ctsl --cc-trailers 20240404180731.7006-3-tanmay@marvell.com
Grabbing thread from lore.kernel.org/all/20240404180731.7006-3-tanmay@marvell.com/t.mbox.gz
Checking for newer revisions
Grabbing search results from lore.kernel.org
Analyzing 3 messages in the thread
Checking attestation on all messages, may take a moment...
---
✓ [PATCH v2 1/2] perf: cs-etm: Fixes in instruction sample synthesis
+ Link: https://lore.kernel.org/r/20240404180731.7006-2-tanmay@marvell.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
✓ [PATCH v2 2/2] perf: cs-etm: Store previous timestamp in packet queue
+ Link: https://lore.kernel.org/r/20240404180731.7006-3-tanmay@marvell.com
+ Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
✓ Signed: DKIM/marvell.com
---
Total patches: 2
---
Cover: ./v2_20240404_tanmay_fix_coresight_instruction_synthesis_logic.cover
Link: https://lore.kernel.org/r/20240404180731.7006-1-tanmay@marvell.com
Base: applies clean to current tree
git checkout -b v2_20240404_tanmay_marvell_com HEAD
git am ./v2_20240404_tanmay_fix_coresight_instruction_synthesis_logic.mbx
⬢[acme@toolbox perf-tools-next]$
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next prev parent reply other threads:[~2024-04-25 18:54 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-04 18:07 [PATCH V2 0/2] Fix Coresight instruction synthesis logic Tanmay Jagdale
2024-04-04 18:07 ` [PATCH V2 1/2] perf: cs-etm: Fixes in instruction sample synthesis Tanmay Jagdale
2024-04-04 18:07 ` [PATCH V2 2/2] perf: cs-etm: Store previous timestamp in packet queue Tanmay Jagdale
2024-04-25 18:54 ` Arnaldo Carvalho de Melo [this message]
2024-04-26 15:07 ` [PATCH V2 0/2] Fix Coresight instruction synthesis logic James Clark
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