From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 19209C25B10 for ; Fri, 10 May 2024 12:11:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=rc7MPWDt/2Gz1Ht33M9OWTmZ7Yjs1C2lEgUouZLXmGk=; b=k00KGQQGfBJwFx gN6NclJesTbmdNm4295Y+r/Hh2tYKzil1Zgn45qj5Ew6LzJxVmM+s9FIHrtjBuC7RmECNzRr0+vLf SvxmmswOrVZT2asPaPycdR+8RHAQPr1qG4Qemm5PgrbfSzTRvBTmetBg8ZZjqE+59ugrbBpDazDg/ AzkVvRPkoYloEIEwHHlic47wpYnEn7R0idqlLiSavY5DpQVd0xypQUOnV1Vav0N8mruX+RFLNJRwZ bAPo/MSMCS9VPTck3FnDCoLar81oU11jgTBXn0lcAU7IYJC/WXNqDglNT73SCa7DItNKlsTVh8pcC pp717d7oqchJ3YMO9sOg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s5P6D-00000005Dr7-36FN; Fri, 10 May 2024 12:11:41 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s5P69-00000005Dou-39Yc for linux-arm-kernel@lists.infradead.org; Fri, 10 May 2024 12:11:39 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 40F8061ED0; Fri, 10 May 2024 12:11:34 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AB2A2C113CC; Fri, 10 May 2024 12:11:32 +0000 (UTC) Date: Fri, 10 May 2024 13:11:30 +0100 From: Catalin Marinas To: Yang Shi Cc: will@kernel.org, scott@os.amperecomputing.com, cl@gentwo.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: mm: force write fault for atomic RMW instructions Message-ID: References: <20240507223558.3039562-1-yang@os.amperecomputing.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240507223558.3039562-1-yang@os.amperecomputing.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240510_051137_967064_0ED80916 X-CRM114-Status: GOOD ( 32.28 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, May 07, 2024 at 03:35:58PM -0700, Yang Shi wrote: > The atomic RMW instructions, for example, ldadd, actually does load + > add + store in one instruction, it may trigger two page faults, the > first fault is a read fault, the second fault is a write fault. > > Some applications use atomic RMW instructions to populate memory, for > example, openjdk uses atomic-add-0 to do pretouch (populate heap memory > at launch time) between v18 and v22. I'd also argue that this should be optimised in openjdk. Is an LDADD more efficient on your hardware than a plain STR? I hope it only does one operation per page rather than per long. There's also MAP_POPULATE that openjdk can use to pre-fault the pages with no additional fault. This would be even more efficient than any store or atomic operation. Not sure the reason for the architecture to report a read fault only on atomics. Looking at the pseudocode, it checks for both but the read permission takes priority. Also in case of a translation fault (which is what we get on the first fault), I think the syndrome write bit is populated as (!read && write), so 0 since 'read' is 1 for atomics. > But the double page fault has some problems: > > 1. Noticeable TLB overhead. The kernel actually installs zero page with > readonly PTE for the read fault. The write fault will trigger a > write-protection fault (CoW). The CoW will allocate a new page and > make the PTE point to the new page, this needs TLB invalidations. The > tlb invalidation and the mandatory memory barriers may incur > significant overhead, particularly on the machines with many cores. I can see why the current behaviour is not ideal but I can't tell why openjdk does it this way either. A bigger hammer would be to implement mm_forbids_zeropage() but this may affect some workloads that rely on sparsely populated large arrays. > diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h > index db1aeacd4cd9..5d5a3fbeecc0 100644 > --- a/arch/arm64/include/asm/insn.h > +++ b/arch/arm64/include/asm/insn.h > @@ -319,6 +319,7 @@ static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \ > * "-" means "don't care" > */ > __AARCH64_INSN_FUNCS(class_branch_sys, 0x1c000000, 0x14000000) > +__AARCH64_INSN_FUNCS(class_atomic, 0x3b200c00, 0x38200000) This looks correct, it covers the LDADD and SWP instructions. However, one concern is whether future architecture versions will add some instructions in this space that are allowed to do a read only operation (e.g. skip writing if the value is the same or fails some comparison). > diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c > index 8251e2fea9c7..f7bceedf5ef3 100644 > --- a/arch/arm64/mm/fault.c > +++ b/arch/arm64/mm/fault.c > @@ -529,6 +529,7 @@ static int __kprobes do_page_fault(unsigned long far, unsigned long esr, > unsigned int mm_flags = FAULT_FLAG_DEFAULT; > unsigned long addr = untagged_addr(far); > struct vm_area_struct *vma; > + unsigned int insn; > > if (kprobe_page_fault(regs, esr)) > return 0; > @@ -586,6 +587,24 @@ static int __kprobes do_page_fault(unsigned long far, unsigned long esr, > if (!vma) > goto lock_mmap; > > + if (mm_flags & (FAULT_FLAG_WRITE | FAULT_FLAG_INSTRUCTION)) > + goto continue_fault; I'd avoid the goto if possible. Even better, move this higher up into the block of if/else statements building the vm_flags and mm_flags. Factor out the checks into a different function - is_el0_atomic_instr() or something. > + > + pagefault_disable(); This prevents recursively entering do_page_fault() but it may be worth testing it with an execute-only permission. > + > + if (get_user(insn, (unsigned int __user *) instruction_pointer(regs))) { > + pagefault_enable(); > + goto continue_fault; > + } > + > + if (aarch64_insn_is_class_atomic(insn)) { > + vm_flags = VM_WRITE; > + mm_flags |= FAULT_FLAG_WRITE; > + } The above would need to check if the fault is coming from a 64-bit user mode, otherwise the decoding wouldn't make sense: if (!user_mode(regs) || compat_user_mode(regs)) return false; (assuming a separate function that checks the above and returns a bool; you'd need to re-enable the page faults) You also need to take care of endianness since the instructions are always little-endian. We use a similar pattern in user_insn_read(): u32 instr; __le32 instr_le; if (get_user(instr_le, (__le32 __user *)instruction_pointer(regs))) return false; instr = le32_to_cpu(instr_le); ... That said, I'm not keen on this kernel workaround. If openjdk decides to improve some security and goes for PROT_EXEC-only mappings of its text sections, the above trick will no longer work. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel