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Wed, 01 May 2024 12:48:17 -0700 (PDT) Received: from ghost ([2601:647:5700:6860:1dcc:e03e:dc61:895d]) by smtp.gmail.com with ESMTPSA id j10-20020a17090276ca00b001dd69aca213sm24321702plt.270.2024.05.01.12.48.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 May 2024 12:48:16 -0700 (PDT) Date: Wed, 1 May 2024 12:48:13 -0700 From: Charlie Jenkins To: Conor Dooley Cc: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Evan Green , =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= , Jonathan Corbet , Shuah Khan , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH v4 07/16] riscv: cpufeature: Extract common elements from extension checking Message-ID: References: <20240426-dev-charlie-support_thead_vector_6_9-v4-0-b692f3c516ec@rivosinc.com> <20240426-dev-charlie-support_thead_vector_6_9-v4-7-b692f3c516ec@rivosinc.com> <20240501-probable-unfunded-746ef6ae1853@spud> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240501-probable-unfunded-746ef6ae1853@spud> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240501_124819_473992_7BE79AC0 X-CRM114-Status: GOOD ( 23.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, May 01, 2024 at 12:37:14PM +0100, Conor Dooley wrote: > On Fri, Apr 26, 2024 at 02:29:21PM -0700, Charlie Jenkins wrote: > > The __riscv_has_extension_likely() and __riscv_has_extension_unlikely() > > functions from the vendor_extensions.h can be used to simplify the > > standard extension checking code as well. Migrate those functions to > > cpufeature.h and reorganize the code in the file to use the functions. > > > > Signed-off-by: Charlie Jenkins > > --- > > arch/riscv/include/asm/cpufeature.h | 78 +++++++++++++++++------------- > > arch/riscv/include/asm/vendor_extensions.h | 28 ----------- > > 2 files changed, 44 insertions(+), 62 deletions(-) > > > > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h > > index fedd479ccfd1..17896ec9ec11 100644 > > --- a/arch/riscv/include/asm/cpufeature.h > > +++ b/arch/riscv/include/asm/cpufeature.h > > @@ -98,59 +98,66 @@ extern bool riscv_isa_fallback; > > > > unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); > > > > +#define EXT_ALL_VENDORS 0 > > It's not really "all vendors", it's standard. Otherwise, this seems all This hooks up into the alternatives: ALTERNATIVE("nop", "j %l[l_yes]", %[vendor], %[ext], 1) Where the "vendor" argument is supposed to be 0 if the alternative is applicable to all vendors. Is there a better way to convey this? - Charlie > grand to me, > Reviewed-by: Conor Dooley > > Cheers, > Conor. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel