From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 00BD0C4345F for ; Fri, 3 May 2024 16:01:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=6xuWoQuDODP7gE3ndWCEwNzUk81kcq991ZOA2I6AXuY=; b=PgbF1HoQodE6gF EAYRMcIypbwV/E6Ub/UJgvphUdDaWtvcnTDYopZr/0nbn4tAPibzeqF+SgEJ8fI4rHpRYSvZ7j4OH Ti8pHjl7zlZLGyD4queDA6iwrsVEhpsBmLUJkcEiP5lnWqAKQv+EasWnBe0In4g56Kjl6W+yTEnRO VwSdE3SJmZxttKKG/JXcu7TZNHusrEJIR/VKA81rEeis+VnhZlJTdUl7tvbUk3QvEVdKsfJHcR/IU GKAtYIU1855JyV89kM1zZGtDA26t6wXHmoc1J9VrFTGMv7OS/wzwDYG8JPxOGtPTT5qWUQ4Vacqs4 MqBKaKPJrkM/o+xQqVhg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s2vLO-0000000H8YV-2XRS; Fri, 03 May 2024 16:01:06 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s2vLH-0000000H8XD-3H32 for linux-arm-kernel@lists.infradead.org; Fri, 03 May 2024 16:01:01 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9C3BD13D5; Fri, 3 May 2024 09:01:23 -0700 (PDT) Received: from FVFF77S0Q05N (unknown [10.57.34.156]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 41A513F793; Fri, 3 May 2024 09:00:52 -0700 (PDT) Date: Fri, 3 May 2024 17:00:49 +0100 From: Mark Rutland To: Liao Chang Cc: catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, oliver.upton@linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, tglx@linutronix.de, ardb@kernel.org, broonie@kernel.org, anshuman.khandual@arm.com, miguel.luis@oracle.com, joey.gouly@arm.com, ryan.roberts@arm.com, jeremy.linton@arm.com, ericchancf@google.com, kristina.martsenko@arm.com, robh@kernel.org, scott@os.amperecomputing.com, songshuaishuai@tinylab.org, shijie@os.amperecomputing.com, akpm@linux-foundation.org, bhe@redhat.com, horms@kernel.org, mhiramat@kernel.org, rmk+kernel@armlinux.org.uk, shahuang@redhat.com, takakura@valinux.co.jp, dianders@chromium.org, swboyd@chromium.org, sumit.garg@linaro.org, frederic@kernel.org, reijiw@google.com, akihiko.odaki@daynix.com, ruanjinjie@huawei.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev Subject: Re: [PATCH v3 1/8] arm64/sysreg: Add definitions for immediate versions of MSR ALLINT Message-ID: References: <20240415064758.3250209-1-liaochang1@huawei.com> <20240415064758.3250209-2-liaochang1@huawei.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240415064758.3250209-2-liaochang1@huawei.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240503_090100_072815_597F123A X-CRM114-Status: GOOD ( 23.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Apr 15, 2024 at 06:47:51AM +0000, Liao Chang wrote: > From: Mark Brown > > Encodings are provided for ALLINT which allow setting of ALLINT.ALLINT > using an immediate rather than requiring that a register be loaded with > the value to write. Since these don't currently fit within the scheme we > have for sysreg generation add manual encodings like we currently do for > other similar registers such as SVCR. > > Since it is required that these immediate versions be encoded with xzr > as the source register provide asm wrapper which ensure this is the > case. > > Signed-off-by: Mark Brown > Signed-off-by: Liao Chang > --- > arch/arm64/include/asm/nmi.h | 27 +++++++++++++++++++++++++++ > arch/arm64/include/asm/sysreg.h | 2 ++ > 2 files changed, 29 insertions(+) > create mode 100644 arch/arm64/include/asm/nmi.h We have helpers for manipulating PSTATE bits; AFAICT we only need the three lines below: ----8<---- diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 9e8999592f3af..5c209d07ae57e 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -94,18 +94,21 @@ #define PSTATE_PAN pstate_field(0, 4) #define PSTATE_UAO pstate_field(0, 3) +#define PSTATE_ALLINT pstate_field(1, 0) #define PSTATE_SSBS pstate_field(3, 1) #define PSTATE_DIT pstate_field(3, 2) #define PSTATE_TCO pstate_field(3, 4) #define SET_PSTATE_PAN(x) SET_PSTATE((x), PAN) #define SET_PSTATE_UAO(x) SET_PSTATE((x), UAO) +#define SET_PSTATE_ALLINT(x) SET_PSTATE((x), ALLINT) #define SET_PSTATE_SSBS(x) SET_PSTATE((x), SSBS) #define SET_PSTATE_DIT(x) SET_PSTATE((x), DIT) #define SET_PSTATE_TCO(x) SET_PSTATE((x), TCO) #define set_pstate_pan(x) asm volatile(SET_PSTATE_PAN(x)) #define set_pstate_uao(x) asm volatile(SET_PSTATE_UAO(x)) +#define set_pstate_allint(x) asm volatile(SET_PSTATE_ALLINT(x)) #define set_pstate_ssbs(x) asm volatile(SET_PSTATE_SSBS(x)) #define set_pstate_dit(x) asm volatile(SET_PSTATE_DIT(x)) ---->8---- The addition of and refrences to and arm64_supports_nmi() don't seem like they should be part of this patch. Mark. > > diff --git a/arch/arm64/include/asm/nmi.h b/arch/arm64/include/asm/nmi.h > new file mode 100644 > index 000000000000..0c566c649485 > --- /dev/null > +++ b/arch/arm64/include/asm/nmi.h > @@ -0,0 +1,27 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (C) 2022 ARM Ltd. > + */ > +#ifndef __ASM_NMI_H > +#define __ASM_NMI_H > + > +#ifndef __ASSEMBLER__ > + > +#include > + > +extern bool arm64_supports_nmi(void); > + > +#endif /* !__ASSEMBLER__ */ > + > +static __always_inline void _allint_clear(void) > +{ > + asm volatile(__msr_s(SYS_ALLINT_CLR, "xzr")); > +} > + > +static __always_inline void _allint_set(void) > +{ > + asm volatile(__msr_s(SYS_ALLINT_SET, "xzr")); > +} > + > +#endif > + > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 9e8999592f3a..b105773c57ca 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -167,6 +167,8 @@ > * System registers, organised loosely by encoding but grouped together > * where the architected name contains an index. e.g. ID_MMFR_EL1. > */ > +#define SYS_ALLINT_CLR sys_reg(0, 1, 4, 0, 0) > +#define SYS_ALLINT_SET sys_reg(0, 1, 4, 1, 0) > #define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3) > #define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3) > #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3) > -- > 2.34.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel