From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0C367C4345F for ; Fri, 3 May 2024 17:15:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=hscQ0zeo/7IidOWjjPVRWLRxxW/8f16CuqjgVv3+l3A=; b=trs3u9Ekv+DcPH x0xmC3pR85Ikad9tBnoIbok7WISqU2Jze89gd8+gkh+Gj82f+eH8glcxSKzGMgzurBBpcBaT85Ixz 3jRaUPhQ+uPnaCv9L4XQsHW4rKN0JtY2fH20FfNECMn8ia1xsjmrkCtgNY9H+42QwT1omniKQ1CVN 9TqYMoS1wvPZQ0NdwylRSIH0Vbsr6Dv1sZwlNvcH4ZaY7RksACnHy6wxAO9a9jf0+DKhMpk+MtoYk dtekWd0ZzEUxa7ULcRG6UUiYvThmQDhzgLEO/z/0FlwmXis8tJPrvmS4h3y7/2RzHL2uWmcFsfJ0W sDqxQelbyUVllLm3wylg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1s2wVG-0000000HLil-3opd; Fri, 03 May 2024 17:15:22 +0000 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1s2wVE-0000000HLhQ-1bAe for linux-arm-kernel@lists.infradead.org; Fri, 03 May 2024 17:15:21 +0000 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-6f44d2b3130so731967b3a.2 for ; Fri, 03 May 2024 10:15:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1714756519; x=1715361319; darn=lists.infradead.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=IR9Dw9o647tpbzebAAxLcMVlSF9mEsNZdLQZ0kKOolM=; b=aqP273S2Ioo8v6sREcNrSB1sCrfcvhBr6n5AUHZ9LlKI4VICSgGFimQecb38OaLaJk LD29jpKLXHOOR75UXuy6W9x+Ucji+WlQ8bmi6UXww+jcl99EBj4mFXMqH4ZfHD8Lm6nX KThzzce7J56R715n5l5nmfHrCQ97ot+FBZCO8x1TFLQ6DDrnnFWcmgua72fjj10ceVmm 6zRJx1mXO5EzGB9F2VFcW09yJXbMDNsKDX2RF96sg9lo0g2mjKY2vQ5DdyRqEwcKr4pA GFSHKfhuWUfSydpjBPQdFoC/uI3VpJu9lZrpythoY6gkPfl3dLsa+28g6vSne7QDfuGG b86Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1714756519; x=1715361319; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=IR9Dw9o647tpbzebAAxLcMVlSF9mEsNZdLQZ0kKOolM=; b=Fp9bBOWn+1fOHcCJDF/is7nX6TKbXOb1PIwrZlENRni0Rh+ONuPymTay8ERcwR59Ei uQwUM3O1mloqSxKNgx8PO/LNhVpdcqgexUnjhDlA42A2E3eM7+rvEBD8Sc95cDzlKpLG flHjqY5zm/QCtqYN0ddcHgY1cX6ibMht6HpVxDBpjwcdnmO5pHNlahgIRh9ILw4SVAfu FkkW530ULIae6yDmW8XOxCYZupVYk7BZ2iljjMzPn864SljfbPskVbtdfOtQ1W+fUyyv phlRluHdcTEeztZ/xckB3KEK4iUC9YJf7DMUSnXdTF2Jouka5y0rDDWcvBBcBq6axyXG IVmQ== X-Forwarded-Encrypted: i=1; AJvYcCVHCoETX4NZXSZcaaPvn13b9zVj3pY2qhaKOVLKNb0KkAVTIFm0kf6ejTVpmaqz2RABbxZzEnc/Umz48N/WR8Mr03NlhVFVKWaH0dhQY7rw4KOglvA= X-Gm-Message-State: AOJu0YyDWSaCBooJnN/ItMcz2Q4rqn9ZtHzas0xVy+sLgWm0qhLByxSw Tb44/UmUJTS9OkeyH2HhUBBg1hOOITOY3Gia5F8NsXI3lG0DFj4bsN99W7yuQHc= X-Google-Smtp-Source: AGHT+IHG3ZemJFTYg6GOZn4rpbMiTAR/x+d8MQq95B86XEU2h2htwHHaFGS8+oRoHKNhlimohWA0fw== X-Received: by 2002:a05:6a00:10cb:b0:6f3:ebc4:4407 with SMTP id d11-20020a056a0010cb00b006f3ebc44407mr3276248pfu.4.1714756519086; Fri, 03 May 2024 10:15:19 -0700 (PDT) Received: from ghost ([2601:647:5700:6860:f8a2:eea3:33:d368]) by smtp.gmail.com with ESMTPSA id b123-20020a62cf81000000b006f45757a5c4sm27256pfg.105.2024.05.03.10.15.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 May 2024 10:15:18 -0700 (PDT) Date: Fri, 3 May 2024 10:15:16 -0700 From: Charlie Jenkins To: Conor Dooley Cc: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Guo Ren , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Conor Dooley , Evan Green , =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= , Jonathan Corbet , Shuah Khan , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH v5 03/17] riscv: vector: Use vlenb from DT Message-ID: References: <20240502-dev-charlie-support_thead_vector_6_9-v5-0-d1b5c013a966@rivosinc.com> <20240502-dev-charlie-support_thead_vector_6_9-v5-3-d1b5c013a966@rivosinc.com> <20240503-zippy-skeletal-e5f63c9f17c1@spud> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240503-zippy-skeletal-e5f63c9f17c1@spud> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240503_101520_466197_7F4FDB05 X-CRM114-Status: GOOD ( 32.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, May 03, 2024 at 05:59:33PM +0100, Conor Dooley wrote: > On Thu, May 02, 2024 at 09:46:38PM -0700, Charlie Jenkins wrote: > > If vlenb is provided in the device tree, prefer that over reading the > > vlenb csr. > > > > Signed-off-by: Charlie Jenkins > > --- > > arch/riscv/include/asm/cpufeature.h | 2 ++ > > arch/riscv/kernel/cpufeature.c | 43 +++++++++++++++++++++++++++++++++++++ > > arch/riscv/kernel/vector.c | 12 ++++++++++- > > 3 files changed, 56 insertions(+), 1 deletion(-) > > > > diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h > > index 347805446151..0c4f08577015 100644 > > --- a/arch/riscv/include/asm/cpufeature.h > > +++ b/arch/riscv/include/asm/cpufeature.h > > @@ -31,6 +31,8 @@ DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo); > > /* Per-cpu ISA extensions. */ > > extern struct riscv_isainfo hart_isa[NR_CPUS]; > > > > +extern u32 riscv_vlenb_of; > > + > > void riscv_user_isa_enable(void); > > > > #if defined(CONFIG_RISCV_MISALIGNED) > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > > index 3ed2359eae35..12c79db0b0bb 100644 > > --- a/arch/riscv/kernel/cpufeature.c > > +++ b/arch/riscv/kernel/cpufeature.c > > @@ -35,6 +35,8 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; > > /* Per-cpu ISA extensions. */ > > struct riscv_isainfo hart_isa[NR_CPUS]; > > > > +u32 riscv_vlenb_of; > > + > > /** > > * riscv_isa_extension_base() - Get base extension word > > * > > @@ -648,6 +650,42 @@ static int __init riscv_isa_fallback_setup(char *__unused) > > early_param("riscv_isa_fallback", riscv_isa_fallback_setup); > > #endif > > > > +static int has_riscv_homogeneous_vlenb(void) > > +{ > > + int cpu; > > + u32 prev_vlenb = 0; > > + u32 vlenb; > > + > > + for_each_possible_cpu(cpu) { > > + struct device_node *cpu_node; > > + > > + cpu_node = of_cpu_device_node_get(cpu); > > + if (!cpu_node) { > > + pr_warn("Unable to find cpu node\n"); > > + return -ENOENT; > > + } > > + > > + if (of_property_read_u32(cpu_node, "riscv,vlenb", &vlenb)) { > > + of_node_put(cpu_node); > > + > > + if (prev_vlenb) > > + return -ENOENT; > > + continue; > > + } > > + > > + if (prev_vlenb && vlenb != prev_vlenb) { > > + of_node_put(cpu_node); > > + return -ENOENT; > > + } > > + > > + prev_vlenb = vlenb; > > + of_node_put(cpu_node); > > + } > > + > > + riscv_vlenb_of = vlenb; > > + return 0; > > +} > > + > > void __init riscv_fill_hwcap(void) > > { > > char print_str[NUM_ALPHA_EXTS + 1]; > > @@ -671,6 +709,11 @@ void __init riscv_fill_hwcap(void) > > pr_info("Falling back to deprecated \"riscv,isa\"\n"); > > riscv_fill_hwcap_from_isa_string(isa2hwcap); > > } > > + > > + if (elf_hwcap & COMPAT_HWCAP_ISA_V && has_riscv_homogeneous_vlenb() < 0) { > > I still think this isn't quite right, as it will emit a warning when > RISCV_ISA_V is disabled. The simplest thing to do probably is just > add an `if (IS_ENABLED(CONFIG_RISCV_ISA_V) return 0` shortcut the to > function? It'll get disabled a few lines later so I think a zero is > safe. That seems like a good idea. It is weird to throw a warning about this even when they have V disabled in the kernel. The DT is improperly formatted since it has heterogeneous vlenb entries and has V enabled, but since the user disabled V in the kernel skipping the warning is reasonable. - Charlie > > > + pr_warn("Unsupported heterogeneous vlen detected, vector extension disabled.\n"); > > + elf_hwcap &= ~COMPAT_HWCAP_ISA_V; > > + } > > } > > > > /* > > diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c > > index 6727d1d3b8f2..e04586cdb7f0 100644 > > --- a/arch/riscv/kernel/vector.c > > +++ b/arch/riscv/kernel/vector.c > > @@ -33,7 +33,17 @@ int riscv_v_setup_vsize(void) > > { > > unsigned long this_vsize; > > > > - /* There are 32 vector registers with vlenb length. */ > > + /* > > + * There are 32 vector registers with vlenb length. > > + * > > + * If the riscv,vlenb property was provided by the firmware, use that > > + * instead of probing the CSRs. > > + */ > > + if (riscv_vlenb_of) { > > + this_vsize = riscv_vlenb_of * 32; > > + return 0; > > + } > > + > > riscv_v_enable(); > > this_vsize = csr_read(CSR_VLENB) * 32; > > riscv_v_disable(); > > > > -- > > 2.44.0 > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel