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Tue, 4 Jun 2024 11:28:07 -0700 Date: Tue, 4 Jun 2024 11:28:05 -0700 From: Nicolin Chen To: Jason Gunthorpe CC: , Joerg Roedel , , Robin Murphy , Will Deacon , Michael Shavit , , Ryan Roberts , Mostafa Saleh Subject: Re: [PATCH 1/7] iommu/arm-smmu-v3: Split struct arm_smmu_strtab_cfg.strtab Message-ID: References: <0-v1-1b720dce51d1+4f44-smmuv3_tidy_jgg@nvidia.com> <1-v1-1b720dce51d1+4f44-smmuv3_tidy_jgg@nvidia.com> <20240604125955.GH19897@nvidia.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240604125955.GH19897@nvidia.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B069:EE_|PH7PR12MB5654:EE_ X-MS-Office365-Filtering-Correlation-Id: 3835a1bf-d283-4a2b-ffae-08dc84c42485 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230031|82310400017|36860700004|376005|1800799015; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?+4PWRLtRoiupg/nbM8o4LGsSsGkCI/r4E4Q/Z1VqPSKRRd//cBCa/kOAkx8X?= =?us-ascii?Q?00hsJRywZAOtENrf5R1nf1HBSSvec7GEKqynZg5b/gZlY99jS/RcFHWEUHKE?= =?us-ascii?Q?KVqvZe3M3Vop8kouyT/jN2PV3VRDixof0+YFGkfIBVMyj63TXJeRE0df+M1P?= =?us-ascii?Q?BVhWIGKy56AvJH+CUWVBWlAI6p5c5/pFWv8nM/t1jQ457K6NqPJP0/QpNrZw?= =?us-ascii?Q?DQ0ws5/cs1Xcj5BrMxK1MeJy/a8dwNJVm/i4kBQ/Q2OLmcnwwHSGmEGrUBDt?= =?us-ascii?Q?PoMDWY/Cqrcbcu8QoKaZi0Mt1XcSZ5CM2jZs8Y7cElmXcwzu+k4JhmD0+yLs?= =?us-ascii?Q?J4J85cGnhAc7oBql7qDNtzaTWC5ohBkSrnUakkyhAT54Jy2A/vOmNIVts9Yh?= =?us-ascii?Q?2aD8sIz01CM3ymNHMI8XzdRLdqYnSxauk9zHXutzurUwOYUfozoXt3CjQtaF?= =?us-ascii?Q?U32c54ZmsrfxtKwxZn0l7H3mEF4EJtkrHAoZKWt5NRrmEoTYcmd1F43xE11G?= =?us-ascii?Q?f4oLYhq/lwLJ5t7MUZtsKvA1HuiTDMGpugt0g5s0nNZBDeAFLupBph+R3gH4?= =?us-ascii?Q?9D5Lt2F3POjiEu8dHZ7g1AzMWwIkh7bbJWl/BNP3H8vBnFy7Izk4+Hl3Ju7Y?= =?us-ascii?Q?dqGfHjcVXwTiQJAgQjBzsqNc9lRrBpht29e1AxuRYFiz5uf4Z/1AOdWC6RmB?= =?us-ascii?Q?fwDg2USlyWXj+t0sWso4I0Fn6OyF5gl79e8lM6snIzs4U/z6rhBIY6yEngVH?= =?us-ascii?Q?UGUYprFRfWnJ9gbHtevRnSjbdL/SKDz1qG5pm5k1GZZvdUQX9QB16YEsf9zO?= =?us-ascii?Q?67gFC1lU4p1iu3kLoLuJTieFBjsvmW/xMO6cK7xZtPeUGSWSwpC9yuVIavuB?= =?us-ascii?Q?QKlOzV3xpzFxU80sHEUqBlMCqaXg6JX36TNtAS2Gg8E0/1dxrmiYj2rZ+2Q1?= =?us-ascii?Q?zoDVZANSdy1QwzJJceVhPxy40v1A1J0990BZeQ7m2XKj/pj2dAHugxoMiUZd?= =?us-ascii?Q?HAargIjSBUJbEJcMj5b5rRI1yrq1ftWXh+1YERXVFDQqEwj33WBiWyghtGy+?= =?us-ascii?Q?u46eLReW6Nuii3YLoYBwPU2Q/HJMfFLRCD0qXegpZ9eYxIKXSzhHRvDBbbLq?= =?us-ascii?Q?75fFjoZiL3cXWxy5PaajNkEUibaQuKxLrCpxUTAMT37Io0eUOnuYmf6CcSRC?= =?us-ascii?Q?kCuHFpjA915GZXYx4cih7T1Y81r0NFnTM7bYUN4ahHgu7MiP1L0jadGDkB4y?= =?us-ascii?Q?uOVUhmWeGTbHl3hQqOPZJNBBaTV7xPmC5pNAJAAMPV6zEOat3Cm6mtWSOxbm?= =?us-ascii?Q?cviPPIXXT6gG1oV71sE66TfxC9pKRH9TjwcghERNK+ZZOvyeCq8i/5IbsZzV?= =?us-ascii?Q?l0DpUKVJN9B5x7Uipsz30sS2famx?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230031)(82310400017)(36860700004)(376005)(1800799015);DIR:OUT;SFP:1101; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Jun 04, 2024 at 09:59:55AM -0300, Jason Gunthorpe wrote: > On Tue, Jun 04, 2024 at 01:32:20AM -0700, Nicolin Chen wrote: > > On Mon, Jun 03, 2024 at 07:31:27PM -0300, Jason Gunthorpe wrote: > > > > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > > > index 1242a086c9f948..4769780259affc 100644 > > > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > > > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > > > @@ -612,7 +610,10 @@ struct arm_smmu_s2_cfg { > > > }; > > > > > > struct arm_smmu_strtab_cfg { > > > - __le64 *strtab; > > > + union { > > > + struct arm_smmu_ste *linear; > > > + __le64 *l1_desc; > > > + } strtab; > > > dma_addr_t strtab_dma; > > > struct arm_smmu_strtab_l1_desc *l1_desc; > > > unsigned int num_l1_ents; > > > > It looks like we have two "l1_desc" ptrs now in the same struct: > > strtab.l1_desc // raw level-1 descriptor memory > > l1_desc // SW array to store level-2 descriptor memory > > > > And it gets a bit more confusing that they even use the same error > > prints in arm_smmu_init_strtab_2lvl()... > > Yeah, I noticed that too, but failed to come with better names.. The > CD has the same issue > > strtab.l1_desc is a pointer to the data structure that the HW fetches > that is the first level of a 2 level strtab, it stores an encoded > dma_addr_t. > > cfg.l1_desc is an array of CPU information for each HW L1 entry, > eventually just being the CPU pointer to the L2 STE table. > > So they are both the l1 array, just one is a CPU pointer and one is a > HW/DMA pointer. > > Let's call strtab.l1_desc --> strtab.l1_table ? Yea. This seems to be good. > > The "struct arm_smmu_strtab_l1_desc" seems to be only used at one > > place in arm_smmu_init_l2_strtab(). So, how about: > > I didn't do it but, it would make some of the maths more obvious > if we encoded the table structure in the types: > > struct arm_smmu_strtab_l2_stes { > struct arm_smmu_ste l2[256]; > }; I personally prefer this one, though why 256? I was also thinking of an alternative by separating linear/2lvl: struct arm_smmu_ste { __le64 data[8]; }; struct arm_smmu_strtab_linear { struct arm_smmu_ste *ste; dma_addr_t ste_dma; }; struct arm_smmu_strtab_l1_desc { // so as to drop TRTAB_L1_DESC_DWORDS __le64 data; }; struct arm_smmu_strtab_l2_stes { struct arm_smmu_ste *ste; }; struct arm_smmu_strtab_l1 { struct arm_smmu_strtab_l1_desc *l1; dma_addr_t l1_dma; struct arm_smmu_strtab_l2_stes *l2; }; struct arm_smmu_device { ... union { struct arm_smmu_strtab_linear linear; struct arm_smmu_strtab_l1 l1; } strtab; ... }; Only arm_smmu_device_reset() really needs strtab_base/_cfg values that we could compute them over there, given that there are quite amount of smmu->features checking already? Thanks Nicolin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel