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charset=us-ascii Content-Disposition: inline In-Reply-To: <20240605-imx95-dts-v3-v6-3-2ce275ed0e80@nxp.com> X-CM-TRANSID: C1UQrADnL0+8jG9mzQ3NCA--.30806S3 X-Coremail-Antispam: 1Uf129KBjvJXoW3Ar4UKFy3WryDGFyxCrW5GFg_yoW3JF45pr 93Z3y7KrykJrZrJry8GwnFyF4UJw4kCr1v9rZrW3W0kw13ZwsFgwnYkrn8JrWqvws8Zw13 JFZrZr47K3WqgaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jYKZXUUUUU= X-Originating-IP: [114.216.76.201] X-CM-SenderInfo: pvkd40hjxrjqh1hdxhhqhw/1tbiGB0BZV6Nn45YdwAAsM X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240616_180931_247224_231A5597 X-CRM114-Status: GOOD ( 14.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jun 05, 2024 at 09:22:50AM +0800, Peng Fan (OSS) wrote: > From: Peng Fan > > Add a minimal dts for i.MX95 19x19 EVK board: > - lpuart1 as console > - sdhc1/2 as storage > > Signed-off-by: Peng Fan > --- > arch/arm64/boot/dts/freescale/Makefile | 1 + > arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts | 200 ++++++++++++++++++++++ > 2 files changed, 201 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile > index 1b1e4db02071..c3fef4e4d8dd 100644 > --- a/arch/arm64/boot/dts/freescale/Makefile > +++ b/arch/arm64/boot/dts/freescale/Makefile > @@ -239,6 +239,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb > dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb > dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb > dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb > +dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb > > imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo > imx8mm-venice-gw72xx-0x-rpidsi-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rpidsi.dtbo > diff --git a/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts > new file mode 100644 > index 000000000000..2c2f3cfbe11a > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts > @@ -0,0 +1,200 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright 2024 NXP > + */ > + > +/dts-v1/; > + > +#include "imx95.dtsi" > + > +/ { > + model = "NXP i.MX95 19X19 board"; > + compatible = "fsl,imx95-19x19-evk", "fsl,imx95"; > + > + aliases { > + mmc0 = &usdhc1; > + mmc1 = &usdhc2; > + serial0 = &lpuart1; > + }; > + > + chosen { > + stdout-path = &lpuart1; > + }; > + > + memory@80000000 { > + device_type = "memory"; > + reg = <0x0 0x80000000 0 0x80000000>; > + }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + linux_cma: linux,cma { > + compatible = "shared-dma-pool"; > + alloc-ranges = <0 0x80000000 0 0x7F000000>; > + size = <0 0x3c000000>; > + linux,cma-default; > + reusable; > + }; > + }; > + > + reg_usdhc2_vmmc: regulator-usdhc2 { > + compatible = "regulator-fixed"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; > + regulator-name = "VDD_SD2_3V3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; > + off-on-delay-us = <12000>; > + enable-active-high; enable-active-high right after line of gpio = <... GPIO_ACTIVE_HIGH>; Shawn > + }; > +}; > + > +&lpuart1 { > + /* console */ > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart1>; > + status = "okay"; > +}; > + > +&mu7 { > + status = "okay"; > +}; > + > +&usdhc1 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; > + pinctrl-0 = <&pinctrl_usdhc1>; > + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; > + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; > + pinctrl-3 = <&pinctrl_usdhc1>; > + bus-width = <8>; > + non-removable; > + no-sdio; > + no-sd; > + status = "okay"; > +}; > + > +&usdhc2 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; > + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; > + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; > + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; > + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; > + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; > + vmmc-supply = <®_usdhc2_vmmc>; > + bus-width = <4>; > + status = "okay"; > +}; > + > +&wdog3 { > + fsl,ext-reset-output; > + status = "okay"; > +}; > + > +&scmi_iomuxc { > + pinctrl_uart1: uart1grp { > + fsl,pins = < > + IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e > + IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e > + >; > + }; > + > + pinctrl_usdhc1: usdhc1grp { > + fsl,pins = < > + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e > + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e > + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e > + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e > + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e > + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e > + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e > + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e > + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e > + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e > + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e > + >; > + }; > + > + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { > + fsl,pins = < > + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e > + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e > + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e > + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e > + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e > + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e > + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e > + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e > + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e > + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e > + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e > + >; > + }; > + > + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { > + fsl,pins = < > + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe > + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe > + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe > + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe > + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe > + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe > + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe > + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe > + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe > + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe > + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe > + >; > + }; > + > + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { > + fsl,pins = < > + IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e > + >; > + }; > + > + pinctrl_usdhc2_gpio: usdhc2gpiogrp { > + fsl,pins = < > + IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e > + >; > + }; > + > + pinctrl_usdhc2: usdhc2grp { > + fsl,pins = < > + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e > + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e > + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e > + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e > + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e > + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e > + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e > + >; > + }; > + > + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { > + fsl,pins = < > + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e > + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e > + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e > + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e > + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e > + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e > + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e > + >; > + }; > + > + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { > + fsl,pins = < > + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe > + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe > + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe > + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe > + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe > + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe > + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e > + >; > + }; > +}; > > -- > 2.37.1 >