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Tue, 9 Jul 2024 11:29:47 -0700 Date: Tue, 9 Jul 2024 11:29:46 -0700 From: Nicolin Chen To: Will Deacon CC: , , , , , , , , , Subject: Re: [PATCH v9 4/6] iommu/arm-smmu-v3: Add CS_NONE quirk for CONFIG_TEGRA241_CMDQV Message-ID: References: <20240702174307.GB4740@willie-the-truck> <20240702184942.GD5167@willie-the-truck> <20240705152721.GA9485@willie-the-truck> <20240708112928.GB11567@willie-the-truck> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7E:EE_|PH0PR12MB7863:EE_ X-MS-Office365-Filtering-Correlation-Id: 9fa985a7-914c-49a2-08e5-08dca04528dc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?gpKXEUFgbKIxkhSOj7SdwDMBiRKg9j7kGVTY3ia0nyBRL9qwOlW0RxLP60cr?= =?us-ascii?Q?/pHra1wgpmLP1rmFUtz3t4t+J1imSd+ovzBRe7fz/B24Jt6BOOK2y57W3mO2?= =?us-ascii?Q?JlrDsMzs6eHvgrQIDe39J/HJII5ALoOPgT6XlMRrrzL4drw8JJADxYzQjyqi?= =?us-ascii?Q?2m4k7FI0478tGK5IJ6GP7oH9NjfqrFLzgP8hccAyNNjD67tkOSkOfKokHBr8?= =?us-ascii?Q?MI+kLiXdYVP2MC1vw6CJ4v1mi8IXSnsNt0/4Ybr3odQhybAuxlWwb5/Pi2+B?= =?us-ascii?Q?TmGpzZEJ7rYbZet3r+wr1Rh8GximOQ/IGPBwj/W/dFyZHt1ZfUj53ss3cBeZ?= =?us-ascii?Q?hnV79iJD+klMa+4jsgB7Mh5EEULXgS4pNTC2yoNfPaGKzO1w9sRawrWo8ZT4?= =?us-ascii?Q?xoBAqQ9ze7xE4UpHb4AJ8fEx+XVxe/Q63rBC+zfIt+bVVtcJxQdDmoaPK+8n?= =?us-ascii?Q?GKKE1uNrK5KJlsF1fMn5kH1J2zP818WVlKBOyEMvOHTWLxJV/9G1yTnw4ow7?= =?us-ascii?Q?ytVp4Ue1TPKPeFYHot0e8gNG0um9J/VvWZgLXAq1vJQPPq1kaxRXZMm1Mgpn?= =?us-ascii?Q?GDNP5jixme1Cmp8SUmx3CV/29A3tUwko6MP+4LQZkzz2LMQ0+s42xzkdil+F?= =?us-ascii?Q?Ogt1cG6eTihC12L70Exh4ZkFnFUSTijZuBqERGtZTy5cbWgiwsNaV0A9c5tb?= =?us-ascii?Q?YEzzNGUwbtMkSRlQi6z3nGfkbKQTPLpgPXBQcw5OyAluhA9Vq5a96kSweu65?= =?us-ascii?Q?EzrPTpDzXWdoqE342HjXjxCtQU++admQ1wwRci36199Pz8huSubF2TZrjNvM?= =?us-ascii?Q?8R1L+0JqMvE6SuuvEgxcLPF40ojqC2HdbTsQUyQPJVLUTxOCieycXxXNkuMf?= =?us-ascii?Q?eY6PzMEH1m3zaN2VfGYbemZABIXcKRBguRHbNj2apcRksw/1OUi+3+9yPnXc?= =?us-ascii?Q?ugJa8d5ovGdRpjxgXFAH//AAPT6s2LshgvnfBuwRBkNOSb0v9PhY6d7+p10m?= =?us-ascii?Q?WuHid2jv1LnzRQC5bG3/nxb96ewMMudnIC+0zG+miYKka9BAk59+3e8/j1mi?= =?us-ascii?Q?l/B9tzWZDN/RgsOnC74l+N7TybJnKqRz+r9u+Eaqqn/OAtLONK93c2Qoxu9n?= =?us-ascii?Q?lHKcoMSCV68kfws8JYvN3ML6hnmXgEaWITrF/9qCla6Ss8EtyqbRtxUMOyjm?= =?us-ascii?Q?FAoZoGGMFyq3mm0clkqQX6HdijM4sQjJdVTc1upHlXbawORnpqILgC9fSIpx?= =?us-ascii?Q?dNXtAi3/NXLJakUTydL1AU94osKSghATh9u0OUZ8C0w+xYLDI58A+zCgkmaw?= =?us-ascii?Q?NMlvplZz275/Pfu7/LmauDU69ZW3XkfnCZ0MMdJs5XXBUy0OqAf4B2yA2Itg?= =?us-ascii?Q?JfDIsPnk/H+AiHsqM7gQ3RdZrBU+Wts76YpSdWECGRsOCDszGTgN1ezMIHYW?= =?us-ascii?Q?eOWLS0enNZDZW23V6+0Lz9NenQLd8a8s?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2024 18:30:07.7057 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9fa985a7-914c-49a2-08e5-08dca04528dc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7863 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240709_113022_547643_EFB5BA1B X-CRM114-Status: GOOD ( 22.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Will, On Mon, Jul 08, 2024 at 11:00:00AM -0700, Nicolin Chen wrote: > On Mon, Jul 08, 2024 at 12:29:28PM +0100, Will Deacon wrote: > > > With that, we cannot avoid an unconditional hard-coding tegra > > > function call even if we switch to an impl design: > > > > > > +static int acpi_smmu_impl_init(u32 model, struct arm_smmu_device *smmu) > > > +{ > > > + /* > > > + * unconditional go through ACPI table to detect if there is a tegra241 > > > + * implementation that extends SMMU with a CMDQV. The probe() will fill > > > + * the smmu->impl pointer upon success. Otherwise, fall back to regular > > > + * SMMU CMDQ. > > > + */ > > > + tegra241_impl_acpi_probe(smmu); > > > > In-line the minimal DSDT parsing to figure out if we're on a Tegra part. > > If it's that bad, put it in a static inline in arm-smmu-v3.h. > > OK. How about the following? > > /* arm-smmu-v3.h */ > static inline void arm_smmu_impl_acpi_dsdt_probe(struct arm_smmu_device *smmu, > struct acpi_iort_node *node) > { > tegra241_cmdqv_acpi_dsdt_probe(smmu, node); > } > > /* arm-smmu-v3.c */ > static int arm_smmu_impl_acpi_probe(struct arm_smmu_device *smmu, > struct acpi_iort_node *node) > { > /* > * DSDT might holds some SMMU extension, so we have no option but to go > * through ACPI tables unconditionally. This probe function should fill > * the smmu->impl pointer upon success. Otherwise, just carry on with a > * standard SMMU. > */ > arm_smmu_impl_acpi_dsdt_probe(smmu, node); > > return 0; > } I have reworked my series and it looks like: ------------------------------------------------------------- @ -627,9 +630,35 @@ struct arm_smmu_strtab_cfg { u32 strtab_base_cfg; }; +struct arm_smmu_impl { + int (*device_reset)(struct arm_smmu_device *smmu); + void (*device_remove)(struct arm_smmu_device *smmu); + struct arm_smmu_cmdq *(*get_secondary_cmdq)(struct arm_smmu_device *smmu, + u8 opcode); +}; + +#ifdef CONFIG_TEGRA241_CMDQV +struct arm_smmu_device * +tegra241_cmdqv_acpi_dsdt_probe(struct arm_smmu_device *smmu, + struct acpi_iort_node *node); +#endif + +static inline struct arm_smmu_device * +arm_smmu_impl_acpi_dsdt_probe(struct arm_smmu_device *smmu, + struct acpi_iort_node *node) +{ +#ifdef CONFIG_TEGRA241_CMDQV + smmu = tegra241_cmdqv_acpi_dsdt_probe(smmu, node); +#endif + return smmu; +} + /* An SMMUv3 instance */ struct arm_smmu_device { struct device *dev; + /* An SMMUv3 implementation */ + const struct arm_smmu_impl *impl; + void __iomem *base; void __iomem *page1; ------------------------------------------------------------- One thing that I want to confirm is about the smmu pointer. I implemented in the way that SMMUv2 driver does, i.e. the passed-in SMMU pointer gets devm_realloc() to &cmdev->smmu. Is it something you would prefer? Thanks Nicolin