From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4F548C2BD09 for ; Mon, 1 Jul 2024 17:07:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=kEqeqn/3iyfM+SGiw8T1vWo5uAX8Xc+FlBFruCr6B2c=; b=CDZET1L2E9XdsUBkgUTWeJKM3b E9fPmG3QB3W9UL4rbijImBc67qSfODo60aMsFZ8+W89KS4t6DZ21D3VC8bOPn4gY4TV7DP6IqdW2s JeEdmeHCknHsNVZIu29JIJVWIN4UIJ4lJU9VkCwYrUSOcPBbdtl41Nl4hRYzI8ujResEpN675rKDa 2BV/X9ew/aJaBx0rJW/tDeY5R0UYEbOhLAMy7ShTdMMmvpK+AWKWJhoIQIyRFMWWZSU1/nfyG6q8M X/13h125eK4DTBbO38YiRZu3hwHptxfuujyH9rLn7JBEE3INLX0Ryb/2WlJ5gkDc+XF2JmqFP9vb8 zc4sQHtw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sOKV1-00000004Faj-39UD; Mon, 01 Jul 2024 17:07:31 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sOKUl-00000004FSc-2Jy5 for linux-arm-kernel@lists.infradead.org; Mon, 01 Jul 2024 17:07:17 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B6209339; Mon, 1 Jul 2024 10:07:39 -0700 (PDT) Received: from J2N7QTR9R3 (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 846AD3F766; Mon, 1 Jul 2024 10:07:11 -0700 (PDT) Date: Mon, 1 Jul 2024 18:07:09 +0100 From: Mark Rutland To: "Rob Herring (Arm)" Cc: Russell King , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Will Deacon , Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , James Clark , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, kvmarm@lists.linux.dev Subject: Re: [PATCH v2 10/12] arm64: perf/kvm: Use a common PMU cycle counter define Message-ID: References: <20240626-arm-pmu-3-9-icntr-v2-0-c9784b4f4065@kernel.org> <20240626-arm-pmu-3-9-icntr-v2-10-c9784b4f4065@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240626-arm-pmu-3-9-icntr-v2-10-c9784b4f4065@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240701_100715_904937_10D3BB5A X-CRM114-Status: GOOD ( 24.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Jun 26, 2024 at 04:32:34PM -0600, Rob Herring (Arm) wrote: > The PMUv3 and KVM code each have a define for the PMU cycle counter > index. Move KVM's define to a shared location and use it for PMUv3 > driver. > > Signed-off-by: Rob Herring (Arm) > --- > v2: > - Move ARMV8_PMU_CYCLE_IDX to linux/perf/arm_pmuv3.h > --- > arch/arm64/kvm/sys_regs.c | 1 + > drivers/perf/arm_pmuv3.c | 19 +++++++------------ > include/kvm/arm_pmu.h | 1 - > include/linux/perf/arm_pmuv3.h | 3 +++ > 4 files changed, 11 insertions(+), 13 deletions(-) Acked-by: Mark Rutland Mark. > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index f8b5db48ea8a..22393ae7ce14 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -18,6 +18,7 @@ > #include > #include > > +#include > #include > #include > #include > diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c > index f771242168f1..f58dff49ea7d 100644 > --- a/drivers/perf/arm_pmuv3.c > +++ b/drivers/perf/arm_pmuv3.c > @@ -451,11 +451,6 @@ static const struct attribute_group armv8_pmuv3_caps_attr_group = { > .attrs = armv8_pmuv3_caps_attrs, > }; > > -/* > - * Perf Events' indices > - */ > -#define ARMV8_IDX_CYCLE_COUNTER 31 > - > /* > * We unconditionally enable ARMv8.5-PMU long event counter support > * (64-bit events) where supported. Indicate if this arm_pmu has long > @@ -574,7 +569,7 @@ static u64 armv8pmu_read_counter(struct perf_event *event) > int idx = hwc->idx; > u64 value; > > - if (idx == ARMV8_IDX_CYCLE_COUNTER) > + if (idx == ARMV8_PMU_CYCLE_IDX) > value = read_pmccntr(); > else > value = armv8pmu_read_hw_counter(event); > @@ -607,7 +602,7 @@ static void armv8pmu_write_counter(struct perf_event *event, u64 value) > > value = armv8pmu_bias_long_counter(event, value); > > - if (idx == ARMV8_IDX_CYCLE_COUNTER) > + if (idx == ARMV8_PMU_CYCLE_IDX) > write_pmccntr(value); > else > armv8pmu_write_hw_counter(event, value); > @@ -644,7 +639,7 @@ static void armv8pmu_write_event_type(struct perf_event *event) > armv8pmu_write_evtype(idx - 1, hwc->config_base); > armv8pmu_write_evtype(idx, chain_evt); > } else { > - if (idx == ARMV8_IDX_CYCLE_COUNTER) > + if (idx == ARMV8_PMU_CYCLE_IDX) > write_pmccfiltr(hwc->config_base); > else > armv8pmu_write_evtype(idx, hwc->config_base); > @@ -772,7 +767,7 @@ static void armv8pmu_enable_user_access(struct arm_pmu *cpu_pmu) > /* Clear any unused counters to avoid leaking their contents */ > for_each_andnot_bit(i, cpu_pmu->cntr_mask, cpuc->used_mask, > ARMPMU_MAX_HWEVENTS) { > - if (i == ARMV8_IDX_CYCLE_COUNTER) > + if (i == ARMV8_PMU_CYCLE_IDX) > write_pmccntr(0); > else > armv8pmu_write_evcntr(i, 0); > @@ -933,8 +928,8 @@ static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc, > /* Always prefer to place a cycle counter into the cycle counter. */ > if ((evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) && > !armv8pmu_event_get_threshold(&event->attr)) { > - if (!test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask)) > - return ARMV8_IDX_CYCLE_COUNTER; > + if (!test_and_set_bit(ARMV8_PMU_CYCLE_IDX, cpuc->used_mask)) > + return ARMV8_PMU_CYCLE_IDX; > else if (armv8pmu_event_is_64bit(event) && > armv8pmu_event_want_user_access(event) && > !armv8pmu_has_long_event(cpu_pmu)) > @@ -1196,7 +1191,7 @@ static void __armv8pmu_probe_pmu(void *info) > 0, FIELD_GET(ARMV8_PMU_PMCR_N, armv8pmu_pmcr_read())); > > /* Add the CPU cycles counter */ > - set_bit(ARMV8_IDX_CYCLE_COUNTER, cpu_pmu->cntr_mask); > + set_bit(ARMV8_PMU_CYCLE_IDX, cpu_pmu->cntr_mask); > > pmceid[0] = pmceid_raw[0] = read_pmceid0(); > pmceid[1] = pmceid_raw[1] = read_pmceid1(); > diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h > index 334d7c5503cf..871067fb2616 100644 > --- a/include/kvm/arm_pmu.h > +++ b/include/kvm/arm_pmu.h > @@ -10,7 +10,6 @@ > #include > #include > > -#define ARMV8_PMU_CYCLE_IDX (ARMV8_PMU_MAX_COUNTERS - 1) > > #if IS_ENABLED(CONFIG_HW_PERF_EVENTS) && IS_ENABLED(CONFIG_KVM) > struct kvm_pmc { > diff --git a/include/linux/perf/arm_pmuv3.h b/include/linux/perf/arm_pmuv3.h > index 792b8e10b72a..f4ec76f725a3 100644 > --- a/include/linux/perf/arm_pmuv3.h > +++ b/include/linux/perf/arm_pmuv3.h > @@ -9,6 +9,9 @@ > #define ARMV8_PMU_MAX_GENERAL_COUNTERS 31 > #define ARMV8_PMU_MAX_COUNTERS 32 > > +#define ARMV8_PMU_CYCLE_IDX 31 > + > + > /* > * Common architectural and microarchitectural event numbers. > */ > > -- > 2.43.0 >