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Tue, 2 Jul 2024 11:19:57 -0700 Date: Tue, 2 Jul 2024 11:19:56 -0700 From: Nicolin Chen To: Will Deacon CC: , , , , , , , , , Subject: Re: [PATCH v9 4/6] iommu/arm-smmu-v3: Add CS_NONE quirk for CONFIG_TEGRA241_CMDQV Message-ID: References: <20240702174307.GB4740@willie-the-truck> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20240702174307.GB4740@willie-the-truck> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001F3:EE_|LV2PR12MB6016:EE_ X-MS-Office365-Filtering-Correlation-Id: aacfebf3-fed4-4671-1707-08dc9ac3a064 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Qu62bWmkV62F+TK72P4IWmeqOCFbMq3cuo01VOlTEc1zcizqjz47trAN1zzm?= =?us-ascii?Q?VvpSv2ivdSpu9Vn/MOHX7eiaV210tFv1RXX4YxOqktxldElKzm75USoaW09b?= =?us-ascii?Q?jXmuTNV5g6SBddHUzn7eJuziYwoSz6GXsEdYEjBWrwPxzupoCz5WXbaaDZPV?= =?us-ascii?Q?/5w2OruDj3j9+dbf/5ZbW61pOZQktqoXJ2Zu3juMdgMryeDk/o4Qun+E1D3u?= =?us-ascii?Q?hmOaCjUF6nLE9LEeuvLtKetBHEhUjDULwxNd6lJD/hrWCxLhJGLIGGQZx3ah?= =?us-ascii?Q?Gc5BmFuJsz4sXx691JNWWz73A8yZ4NqfYTeleq5olOF+bbmDtMt/kOeXsIdR?= =?us-ascii?Q?qT2KQy+01AumbfyLi9Mn5shTW+BqG8/CtuEVaGLN9YaKFgAwsF3w1QOK2jaZ?= =?us-ascii?Q?k0vaejKQBPRPJLT7VPc4yPLYjZKe95piVdsTW1AcB/TiOwVpHqoP3A1p//o7?= =?us-ascii?Q?06sG27seMTm19J/lqCmz3yKqwmqU6t+gIDRQA+iggWtB8O//m3nVkSUoVG67?= =?us-ascii?Q?q1BTm+BDrSg4F9CciKtUAFITQuD2qaypluaMVB1Q0LwH8D8du/CyZsn3VQXM?= =?us-ascii?Q?cHis8QJbqS91EFH2CstZN6V0/C70/+3Uu37b7NxAREsva4PbQqsyNYq8SiR3?= =?us-ascii?Q?Ngu9aCZ5xBfzIyuaEBDcy7ViY2mr9xBccQJimj85HW4acgJyFYxsKmoi4mcX?= =?us-ascii?Q?miCMBjNbra7KxSPKpJbCWhFWFO47Jh7tilbnr03/kAZLA6x+TCIW9DtTE5Bb?= =?us-ascii?Q?NZMu/KlP2u06NUtolChoSQUesiSTqEW00wcwNsIBMdKhAAWtP5T3ZqI0I2WU?= =?us-ascii?Q?PwdN5vq3YvEDer9G/ZzyQKBdAq2B83YU5tNcF14HUOd297NGpMi5pLMTPFgq?= =?us-ascii?Q?HDjUDVWEUz9FbVDUBjnmZ9tl2IQYTMNr5D28rNzvagpmAMJ37t45SXvugdRy?= =?us-ascii?Q?ZQLJxtUBXWZiv8fd0rLgsrL2F75a4zLPzQTO2FoM89GwxKBT4NdnPtvZ5Zkt?= =?us-ascii?Q?BRM2LKtO9oAioGOSOG0QueW9o3hyUPLnZNPJNyXiHNfGQ8uVw5L+/3a68eGI?= =?us-ascii?Q?qlBBG37Oqhnb46/qfasH6npqSrRlfGiRLq8lHiHUh7H3BcZBeFo90vwQJxNA?= =?us-ascii?Q?jqtpz5Qz6wJCAWJBvcviF12+9WLgWEVNTpLgSl10i8UHo8r8V+9s1A0MoX5q?= =?us-ascii?Q?H198JdH3ZYNZ3ZkU0cx7BoedV4nMOgpe2BeWH4jpRTc7SC3YYtiDST/5KucA?= =?us-ascii?Q?mF/L9FYMcz8JxfsNC1p1JZk7Nn11i4UwdzT9/zV23I0Xdtu+45CtKJeOF+j3?= =?us-ascii?Q?liEACfxp4YncJCR901Q/QidaKnse+xZptMW1Vzp2vDKcsQyMbNZeA/mI4Sum?= =?us-ascii?Q?nOhWcs97RVbQrOgwzB4tZY7dvWWTYXnSCyR2M8qllFy56yOWmRzHXKk/i20H?= =?us-ascii?Q?oPnzWeqh5lGQ5Sxwzk5RMAGl+LVqnuT9?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Jul 2024 18:20:17.9825 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aacfebf3-fed4-4671-1707-08dc9ac3a064 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001F3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB6016 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240702_112023_831585_D145DAB2 X-CRM114-Status: GOOD ( 24.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Will, On Tue, Jul 02, 2024 at 06:43:07PM +0100, Will Deacon wrote: > On Wed, Jun 12, 2024 at 02:45:31PM -0700, Nicolin Chen wrote: > > The CMDQV extension in NVIDIA Tegra241 SoC only supports CS_NONE in the > > CS field of CMD_SYNC. Add a quirk flag to accommodate that. > > > > Reviewed-by: Jason Gunthorpe > > Signed-off-by: Nicolin Chen > > --- > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 8 +++++++- > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 +++ > > 2 files changed, 10 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > index c864c634cd23..ba0e24d5ffbf 100644 > > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > @@ -345,6 +345,11 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, > > FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH) | > > FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB); > > > > + if (q->quirks & CMDQ_QUIRK_SYNC_CS_NONE_ONLY) { > > + cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_NONE); > > + return; > > + } > > + > > if (!(smmu->options & ARM_SMMU_OPT_MSIPOLL)) { > > cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); > > return; > > @@ -690,7 +695,8 @@ static int arm_smmu_cmdq_poll_until_sync(struct arm_smmu_device *smmu, > > struct arm_smmu_cmdq *cmdq, > > struct arm_smmu_ll_queue *llq) > > { > > - if (smmu->options & ARM_SMMU_OPT_MSIPOLL) > > + if (smmu->options & ARM_SMMU_OPT_MSIPOLL && > > + !(cmdq->q.quirks & CMDQ_QUIRK_SYNC_CS_NONE_ONLY)) > > return __arm_smmu_cmdq_poll_until_msi(smmu, cmdq, llq); > > > > return __arm_smmu_cmdq_poll_until_consumed(smmu, cmdq, llq); > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > > index 180c0b1e0658..01227c0de290 100644 > > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > > @@ -543,6 +543,9 @@ struct arm_smmu_queue { > > > > u32 __iomem *prod_reg; > > u32 __iomem *cons_reg; > > + > > +#define CMDQ_QUIRK_SYNC_CS_NONE_ONLY BIT(0) /* CMD_SYNC CS field supports CS_NONE only */ > > + u32 quirks; > > Please can you use the existing smmu->options field instead of adding > another place to track quirks? Or do you need this only for some of the > queues for a given SMMU device? VCMDQs are extension of a regular SMMU (with its own CMDQ). So, SMMU CMDQ still supports SIG_IRQ for the CS field, while VCMDQs could only support SIG_NONE. In another word, this quirk is not per SMMU but per Queue. I can highlight this in the commit message, if that would make it clear. Thanks Nicolin