From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D7B4C38150 for ; Fri, 5 Jul 2024 18:25:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=BCVoupR77j6ZaMoEHqyW5AAThzIIzGkFt8d0uyq5EsU=; b=08iv6z30gLSy/u3Jm9txDROHXl wQfncsDNaC50oHpc8sZdk55DVfuj9EfRUg1UsMDokuq1YVMSn2L1cuDwBhYE2ir0BgvNNJkH+2HqT 2clUuV0BZBTI9QHr3aPd/zhbDR5IBC5R6Jg+EComm+c0UE5zMDt582vk4AW5Ir/SSltkgdyN+rW9Y iiAGroXTeHxx703Ip2O7b+dDbgo3ktpTBGHfZJLWyShWeVFj3l/yJRJwNbp5HmbDf1qM9AOuP4oYk f9R6nKzU98PrjR+1qLDtaMCZKw2ws+EM2MDKFrUs9r74MTKeG9/Uly4EnYixOdhnStAGvxtL1S4ym My1k3HUQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sPncT-0000000GdEJ-0qP6; Fri, 05 Jul 2024 18:25:17 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sPncD-0000000GdAs-0GPi for linux-arm-kernel@lists.infradead.org; Fri, 05 Jul 2024 18:25:03 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F3AF8DA7; Fri, 5 Jul 2024 11:25:24 -0700 (PDT) Received: from arm.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DF7EB3F73B; Fri, 5 Jul 2024 11:24:58 -0700 (PDT) Date: Fri, 5 Jul 2024 19:24:56 +0100 From: Catalin Marinas To: "Christoph Lameter (Ampere)" Cc: Yang Shi , will@kernel.org, anshuman.khandual@arm.com, david@redhat.com, scott@os.amperecomputing.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [v5 PATCH] arm64: mm: force write fault for atomic RMW instructions Message-ID: References: <20240626191830.3819324-1-yang@os.amperecomputing.com> <773c8be7-eb73-010c-acea-1c2fefd65b84@gentwo.org> <200c5d06-c551-4847-adaf-287750e6aac4@os.amperecomputing.com> <1689cd26-514a-4d72-a1bd-b67357aab3e0@os.amperecomputing.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240705_112501_207059_A97A9C3E X-CRM114-Status: GOOD ( 28.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jul 05, 2024 at 10:05:29AM -0700, Christoph Lameter (Ampere) wrote: > On Thu, 4 Jul 2024, Catalin Marinas wrote: > > It could be worked around with a new flavour of get_user() that uses the > > non-T LDR instruction and the user mapping is readable by the kernel > > (that's the case with EPAN, prior to PIE and I think we can change this > > for PIE configurations as well). But it adds to the complexity of this > > patch when the kernel already offers a MADV_POPULATE_WRITE solution. > > The use of MADV_POPULATE_WRITE here is arch specific and not a general > solution. It requires specialized knowledge and research before someone can > figure out that this particular trick is required on Linux ARM64 processors. > The builders need to detect this special situation in the build process and > activate this workaround. Not really, see this OpenJDK commit: https://github.com/openjdk/jdk/commit/a65a89522d2f24b1767e1c74f6689a22ea32ca6a There's nothing about arm64 in there and it looks like the code prefers MADV_POPULATE_WRITE if THPs are enabled (which is the case in all enterprise distros). I can't tell whether the change was made to work around the arm64 behaviour, there's no commit log (it was contributed by Ampere). There's a separate thread with the mm folk on the THP behaviour for pmd_none() vs pmd mapping the zero huge page but it is more portable for OpenJDK to use madvise() than guess the kernel behaviour and touch small pages or a single large pages. Even if one claims that atomic_add(0) is portable across operating systems, the OpenJDK code was already treating Linux as a special case in the presence of THP. > It would be much simpler to just merge the patch and be done with it. > Otherwise this issue will continue to cause uncountably many hours of > anguish for sysadmins and developers all over the Linux ecosystem trying to > figure out what in the world is going on with ARM. People will be happy until one enables execute-only ELF text sections in a distro and all that opcode parsing will add considerable overhead for many read faults (those with a writeable vma). I'd also like to understand (probably have to re-read the older threads) whether the overhead is caused mostly by the double fault or the actual breaking of a THP. For the latter, the mm folk are willing to change the behaviour so that pmd_none() and pmd to the zero high page are treated similarly (i.e. allocate a huge page on write fault). If that's good enough, I'd rather not merge this patch (or some form of it) and wait for a proper fix in hardware in the future. Just to be clear, there are still potential issues to address (or understand the impact of) in this patch with exec-only mappings and the performance gain _after_ the THP behaviour changed in the mm code. We can make a call once we have more data but, TBH, my inclination is towards 'no' given that OpenJDK already support madvise() and it's not arm64 specific. -- Catalin