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Fri, 5 Jul 2024 17:32:25 -0700 Date: Fri, 5 Jul 2024 17:32:24 -0700 From: Nicolin Chen To: Will Deacon CC: , , , , , , , , , Subject: Re: [PATCH v9 4/6] iommu/arm-smmu-v3: Add CS_NONE quirk for CONFIG_TEGRA241_CMDQV Message-ID: References: <20240702174307.GB4740@willie-the-truck> <20240702184942.GD5167@willie-the-truck> <20240705152721.GA9485@willie-the-truck> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FC:EE_|DM4PR12MB8474:EE_ X-MS-Office365-Filtering-Correlation-Id: 34b6418e-61d1-4477-5696-08dc9d5326ef X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?K5Qs5BY1NVkg/P8LjAtvWw7Yw6EqHwST3QcQ/JnJsaH2ePcP/u4dNSVlZFBz?= =?us-ascii?Q?2bnT4zTKFWHzmFzEvYqmZ/nhgVxuj+EJf1pcT0NsHThmePgVQtOuUY8paxgY?= =?us-ascii?Q?z95s3s5QMg5ZgtLsNzFCH4Zj75eY0Viv27/NSqJEgdjTNbAIiqFrCRAISG7Z?= =?us-ascii?Q?Tlr6lGBqes0ownrhM8KXi2qAOslJjUMj9gelcaKYERAnuWzyjnmFdb44tMym?= =?us-ascii?Q?GOIPaQ9+WdrxGmjMgGiJoR5+8s7ynZey1rLizV3i1t4RwK13fHRe8dyO1iaY?= =?us-ascii?Q?jlx1FJFFMjGL1xthzBoFjYOWdFn68i6wmZkUOFdz2G1bZIoYB+eQIwkYGaNk?= =?us-ascii?Q?zhVzg6c/HoLSSIIKfUPRyRktGVjmgKws03cqCoSrilwMAlt8s41Mz+6TrTHs?= =?us-ascii?Q?Xy2f/Rw1gmoTB+H1uFFcxXaTgyejp7MVi0zu1Hfqi2iEDw9Vp3Eli+Ib8PYG?= =?us-ascii?Q?YTiiC0ONt6ZCVgpHlP3T3IJ1d5oi967u/vbARLrxrksSG4dvsOTHGGcFdxod?= =?us-ascii?Q?sFHImd3fvzr3PjSrKTjmQbn+CqoGW9a0qPwfUJBWwr3NCB+0H8l6qT1K65gS?= =?us-ascii?Q?TQnGVnmse95y1zgsqa9Bs5ymiWYNkh56UeVL0YdgIiJiAntW6DnjxJbIS5Mk?= =?us-ascii?Q?F7MUzCVWGpxbp1/vYJnEe4OeS7aYBabQtFBakf0GDvOXYdt+TgEnNEQf0kYI?= =?us-ascii?Q?ydzxgzN4RqoXa6gnKJWnPXv7W9JgyezqF3U4R9VFOs4zX/QtiYj2ftFXmnG9?= =?us-ascii?Q?iW2ZyqZPBHtWTY/btBkhsDpwzDKDTlPIwKWry7kbwyAHyXtoouu8RBIM2OHD?= =?us-ascii?Q?mKWfLffX+FWjJaaYkgtnXj2HPFH6Z8MoNvO2evJ6AW3b+GCRGXoSGmxBzsa3?= =?us-ascii?Q?PF/mJSG395IbhKdy/8YdroKb02NNfa4A5uBn/gGBSTgMoZFakYebumjEbnyB?= =?us-ascii?Q?ns3NXw9WABk+FjgmTPufH86XclMImFq9rTtTQnkG2SdudZd1q0wAkF7X1FoL?= =?us-ascii?Q?Kx3kj2PBvg5zv5j1os2i1x14G+mZfmTYk2FqgC9e85rAywETTzuuew0uADDJ?= =?us-ascii?Q?D3SuF2EL0IYCqdzFUey1X4buIqsAswEX9ATgkX5wDfUrKh2iTMlShzTPOjWP?= =?us-ascii?Q?9vLl6E4wcpw4SnQQQBgUmOL+quM9tndcTQB1mhr2LyZ1udbKcOkk2Cf5zw3s?= =?us-ascii?Q?Li9wYrVgWpBPTMARMt/YYwz98hG4eFrpDw5L4Ukx7Zl4CKeSaT2T+QHEXceV?= =?us-ascii?Q?0G+ERhgaG4yjAm1OX5yi4I+po/N7A2buwAln2c352aYQx80p8JFrTsdUfwPZ?= =?us-ascii?Q?mtqoo8Luy/XGY6kGWpVxgy2rhZPsASSgsZ8wZl9RFi5CwSnMXPxACFKeCNW1?= =?us-ascii?Q?n2vPQLpaZ0laUy5kNgWt/eP4soNSSkH4OKWQohdT1RURAmnnlXLOii1J35Dz?= =?us-ascii?Q?mWMic8+bCZNt9J1yqIFJ7uJG2/tQ41D1?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jul 2024 00:32:43.8802 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 34b6418e-61d1-4477-5696-08dc9d5326ef X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FC.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8474 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240705_173250_506811_AC931306 X-CRM114-Status: GOOD ( 31.99 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jul 05, 2024 at 11:10:47AM -0700, Nicolin Chen wrote: > Hi Will, > > On Fri, Jul 05, 2024 at 04:27:21PM +0100, Will Deacon wrote: > > On Tue, Jul 02, 2024 at 01:10:19PM -0700, Nicolin Chen wrote: > > > On Tue, Jul 02, 2024 at 12:47:14PM -0700, Nicolin Chen wrote: > > > > @@ -345,6 +345,11 @@ static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, > > > > FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH) | > > > > FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB); > > > > > > > > + if (cmdq->type == TEGRA241_VCMDQ) { > > > > + cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_NONE); > > > > + return; > > > > + } > > > > + > > > > if (!(smmu->options & ARM_SMMU_OPT_MSIPOLL)) { > > > > cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); > > > > return; > > > > @@ -690,7 +695,8 @@ static int arm_smmu_cmdq_poll_until_sync(struct arm_smmu_device *smmu, > > > > struct arm_smmu_cmdq *cmdq, > > > > struct arm_smmu_ll_queue *llq) > > > > { > > > > - if (smmu->options & ARM_SMMU_OPT_MSIPOLL) > > > > + if (smmu->options & ARM_SMMU_OPT_MSIPOLL && > > > > + cmdq->type != TEGRA241_VCMDQ) { > > > > return __arm_smmu_cmdq_poll_until_msi(smmu, cmdq, llq); > > > > > > > > -------------------------------------------------------------- > > > > > > > > Would you prefer this one? I feel CMDQ_QUIRK_SYNC_CS_NONE_ONLY > > > > is more general looking though.. > > > > > > And we would need some additional lines of comments for the two > > > pieces above, explaining why TEGRA241_VCMDQ type needs the first > > > one while bypasses the second one. Again, it feels even worse :( > > > > I hacked the code around a bit this afternoon. Please can you see if: > > > > https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/log/?h=for-nicolin/grace-vcmdq-wip > > > > does roughly what you need? > > I appreciate the patch. Yet, we cannot use IORT's model field. > This would need to go through IORT documentation, for A. And B, > we had a very long discussion with ARM (Robin was there) years > ago, and concluded that this CMDQV would not be a model in IORT > but a DSDT node as an extension. So, this is firm... > > With that, we cannot avoid an unconditional hard-coding tegra > function call even if we switch to an impl design: > > +static int acpi_smmu_impl_init(u32 model, struct arm_smmu_device *smmu) > +{ > + /* > + * unconditional go through ACPI table to detect if there is a tegra241 > + * implementation that extends SMMU with a CMDQV. The probe() will fill > + * the smmu->impl pointer upon success. Otherwise, fall back to regular > + * SMMU CMDQ. > + */ > + tegra241_impl_acpi_probe(smmu); > + return 0; > +} > > As for arm_smmu_cmdq_needs_busy_polling, it doesn't really look > very optimal to me. But if you insist on having an smmu option, > we still have to take in the PATCH-3 in this series, enforcing > an arm_smmu_cmdq_build_sync_cmd() call in the IRQ handler too. > So, it would eventually look like [attachment]. Please ignore the attachment. Since we are adding arm_smmu_impl, I figure that we could add an arm_smmu_cmdq_impl too. There's an another small feature that I didn't implement in this v9, while being able to benefit from a cmdq impl now. The impl can also hold a boolean busy_polling, so we won't need a global smmu option. I will send a new version asap, though I am not sure if we can still make it to this cycle that we hoped for :-/ Thanks Nicolin