Re: [PATCH v1 1/4] dt-bindings: imx6q-pcie: Add reg-name "dbi2" and "atu" for i.MX8M PCIe Endpoint

[Frank Li <Frank.li@nxp.com>]

On Mon, Jul 22, 2024 at 05:37:14PM +0100, Conor Dooley wrote:
> On Mon, Jul 22, 2024 at 03:56:16PM +0800, Richard Zhu wrote:
> > Add reg-name: "dbi2", "atu" for i.MX8M PCIe Endpoint.
> > 
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > ---
> >  .../devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml  | 13 +++++++++----
> >  1 file changed, 9 insertions(+), 4 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
> > index a06f75df8458..309e8953dc91 100644
> > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
> > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
> > @@ -65,11 +65,13 @@ allOf:
> >      then:
> >        properties:
> >          reg:
> > -          minItems: 2
> > -          maxItems: 2
> > +          minItems: 4
> > +          maxItems: 4
> >          reg-names:
> >            items:
> >              - const: dbi
> > +            - const: dbi2
> > +            - const: atu
> 
> New properties in the middle of the list is potentially an ABI break.
> Why not add them at the end?

Because it ref to snps,dw-pcie-ep.yaml, which already defined the reg
name orders. we using reg-names to get reg resource, I don't think it break
the ABI. Driver already auto detect both 'dbi2' or no 'dbi2' case.

Frank

> 
> >              - const: addr_space
> >  
> >    - if:
> > @@ -129,8 +131,11 @@ examples:
> >  
> >      pcie_ep: pcie-ep@33800000 {
> >        compatible = "fsl,imx8mp-pcie-ep";
> > -      reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;
> > -      reg-names = "dbi", "addr_space";
> > +      reg = <0x33800000 0x100000>,
> > +            <0x33900000 0x100000>,
> > +            <0x33b00000 0x100000>,
> > +            <0x18000000 0x8000000>;
> > +      reg-names = "dbi", "dbi2", "atu", "addr_space";
> >        clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> >                 <&clk IMX8MP_CLK_HSIO_AXI>,
> >                 <&clk IMX8MP_CLK_PCIE_ROOT>;
> > -- 
> > 2.37.1
> >