From: Alexandru Elisei <alexandru.elisei@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
kvm@vger.kernel.org, James Morse <james.morse@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Zenghui Yu <yuzenghui@huawei.com>,
Joey Gouly <joey.gouly@arm.com>
Subject: Re: [PATCH 08/12] KVM: arm64: nv: Add emulation of AT S12E{0,1}{R,W}
Date: Thu, 18 Jul 2024 16:10:20 +0100 [thread overview]
Message-ID: <ZpkwXFrhcFB1x0nD@raptor> (raw)
In-Reply-To: <20240625133508.259829-9-maz@kernel.org>
Hi,
On Tue, Jun 25, 2024 at 02:35:07PM +0100, Marc Zyngier wrote:
> On the face of it, AT S12E{0,1}{R,W} is pretty simple. It is the
> combination of AT S1E{0,1}{R,W}, followed by an extra S2 walk.
>
> However, there is a great deal of complexity coming from combining
> the S1 and S2 attributes to report something consistent in PAR_EL1.
>
> This is an absolute mine field, and I have a splitting headache.
>
> [..]
> +static u8 compute_sh(u8 attr, u64 desc)
> +{
> + /* Any form of device, as well as NC has SH[1:0]=0b10 */
> + if (MEMATTR_IS_DEVICE(attr) || attr == MEMATTR(NC, NC))
> + return 0b10;
> +
> + return FIELD_GET(PTE_SHARED, desc) == 0b11 ? 0b11 : 0b10;
If shareability is 0b00 (non-shareable), the PAR_EL1.SH field will be 0b10
(outer-shareable), which seems to be contradicting PAREncodeShareability().
> +}
> +
> +static u64 compute_par_s12(struct kvm_vcpu *vcpu, u64 s1_par,
> + struct kvm_s2_trans *tr)
> +{
> + u8 s1_parattr, s2_memattr, final_attr;
> + u64 par;
> +
> + /* If S2 has failed to translate, report the damage */
> + if (tr->esr) {
> + par = SYS_PAR_EL1_RES1;
> + par |= SYS_PAR_EL1_F;
> + par |= SYS_PAR_EL1_S;
> + par |= FIELD_PREP(SYS_PAR_EL1_FST, tr->esr);
> + return par;
> + }
> +
> + s1_parattr = FIELD_GET(SYS_PAR_EL1_ATTR, s1_par);
> + s2_memattr = FIELD_GET(GENMASK(5, 2), tr->desc);
> +
> + if (__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_FWB) {
> + if (!kvm_has_feat(vcpu->kvm, ID_AA64PFR2_EL1, MTEPERM, IMP))
> + s2_memattr &= ~BIT(3);
> +
> + /* Combination of R_VRJSW and R_RHWZM */
> + switch (s2_memattr) {
> + case 0b0101:
> + if (MEMATTR_IS_DEVICE(s1_parattr))
> + final_attr = s1_parattr;
> + else
> + final_attr = MEMATTR(NC, NC);
> + break;
> + case 0b0110:
> + case 0b1110:
> + final_attr = MEMATTR(WbRaWa, WbRaWa);
> + break;
> + case 0b0111:
> + case 0b1111:
> + /* Preserve S1 attribute */
> + final_attr = s1_parattr;
> + break;
> + case 0b0100:
> + case 0b1100:
> + case 0b1101:
> + /* Reserved, do something non-silly */
> + final_attr = s1_parattr;
> + break;
> + default:
> + /* MemAttr[2]=0, Device from S2 */
> + final_attr = s2_memattr & GENMASK(1,0) << 2;
> + }
> + } else {
> + /* Combination of R_HMNDG, R_TNHFM and R_GQFSF */
> + u8 s2_parattr = s2_memattr_to_attr(s2_memattr);
> +
> + if (MEMATTR_IS_DEVICE(s1_parattr) ||
> + MEMATTR_IS_DEVICE(s2_parattr)) {
> + final_attr = min(s1_parattr, s2_parattr);
> + } else {
> + /* At this stage, this is memory vs memory */
> + final_attr = combine_s1_s2_attr(s1_parattr & 0xf,
> + s2_parattr & 0xf);
> + final_attr |= combine_s1_s2_attr(s1_parattr >> 4,
> + s2_parattr >> 4) << 4;
> + }
> + }
> +
> + if ((__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_CD) &&
> + !MEMATTR_IS_DEVICE(final_attr))
> + final_attr = MEMATTR(NC, NC);
> +
> + par = FIELD_PREP(SYS_PAR_EL1_ATTR, final_attr);
> + par |= tr->output & GENMASK(47, 12);
> + par |= FIELD_PREP(SYS_PAR_EL1_SH,
> + compute_sh(final_attr, tr->desc));
> +
> + return par;
>
It seems that the code doesn't combine shareability attributes, as per rule
RGDTNP and S2CombineS1MemAttrs() or S2ApplyFWBMemAttrs(), which both end up
calling S2CombineS1Shareability().
Thanks,
Alex
next prev parent reply other threads:[~2024-07-18 15:11 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-25 13:34 [PATCH 00/12] KVM: arm64: nv: Add support for address translation instructions Marc Zyngier
2024-06-25 13:35 ` [PATCH 01/12] arm64: Add missing APTable and TCR_ELx.HPD masks Marc Zyngier
2024-07-12 8:32 ` Anshuman Khandual
2024-07-13 8:04 ` Marc Zyngier
2024-06-25 13:35 ` [PATCH 02/12] arm64: Add PAR_EL1 field description Marc Zyngier
2024-07-12 7:06 ` Anshuman Khandual
2024-07-13 7:56 ` Marc Zyngier
2024-06-25 13:35 ` [PATCH 03/12] KVM: arm64: nv: Turn upper_attr for S2 walk into the full descriptor Marc Zyngier
2024-06-25 13:35 ` [PATCH 04/12] KVM: arm64: nv: Honor absence of FEAT_PAN2 Marc Zyngier
2024-07-12 8:40 ` Anshuman Khandual
2024-06-25 13:35 ` [PATCH 05/12] KVM: arm64: make kvm_at() take an OP_AT_* Marc Zyngier
2024-07-12 8:52 ` Anshuman Khandual
2024-06-25 13:35 ` [PATCH 06/12] KVM: arm64: nv: Add basic emulation of AT S1E{0,1}{R,W}[P] Marc Zyngier
2024-06-25 13:35 ` [PATCH 07/12] KVM: arm64: nv: Add basic emulation of AT S1E2{R,W} Marc Zyngier
2024-06-25 13:35 ` [PATCH 08/12] KVM: arm64: nv: Add emulation of AT S12E{0,1}{R,W} Marc Zyngier
2024-07-18 15:10 ` Alexandru Elisei [this message]
2024-07-20 9:49 ` Marc Zyngier
2024-07-22 10:33 ` Alexandru Elisei
2024-06-25 13:35 ` [PATCH 09/12] KVM: arm64: nv: Make ps_to_output_size() generally available Marc Zyngier
2024-07-08 16:28 ` [PATCH 00/12] KVM: arm64: nv: Add support for address translation instructions Alexandru Elisei
2024-07-08 17:00 ` Marc Zyngier
2024-07-08 16:57 ` [PATCH 10/12] KVM: arm64: nv: Add SW walker for AT S1 emulation Marc Zyngier
2024-07-08 16:57 ` [PATCH 11/12] KVM: arm64: nv: Plumb handling of AT S1* traps from EL2 Marc Zyngier
2024-07-08 16:58 ` [PATCH 12/12] KVM: arm64: nv: Add support for FEAT_ATS1A Marc Zyngier
2024-07-10 15:12 ` [PATCH 10/12] KVM: arm64: nv: Add SW walker for AT S1 emulation Alexandru Elisei
2024-07-11 8:05 ` Marc Zyngier
2024-07-11 10:56 ` Alexandru Elisei
2024-07-11 12:16 ` Marc Zyngier
2024-07-15 15:30 ` Alexandru Elisei
2024-07-18 11:37 ` Marc Zyngier
2024-07-18 15:16 ` Alexandru Elisei
2024-07-20 13:49 ` Marc Zyngier
2024-07-22 10:53 ` Alexandru Elisei
2024-07-22 15:25 ` Marc Zyngier
2024-07-23 8:57 ` Alexandru Elisei
2024-07-25 14:16 ` Alexandru Elisei
2024-07-25 14:30 ` Marc Zyngier
2024-07-25 15:13 ` Alexandru Elisei
2024-07-25 15:33 ` Marc Zyngier
2024-07-29 15:26 ` Alexandru Elisei
2024-07-31 8:55 ` Marc Zyngier
2024-07-31 9:53 ` Alexandru Elisei
2024-07-31 10:18 ` Marc Zyngier
2024-07-31 10:28 ` Alexandru Elisei
2024-07-31 14:33 ` Alexandru Elisei
2024-07-31 15:43 ` Marc Zyngier
2024-07-31 16:05 ` Alexandru Elisei
2024-07-31 10:05 ` [PATCH 00/12] KVM: arm64: nv: Add support for address translation instructions Alexandru Elisei
2024-07-31 11:02 ` Marc Zyngier
2024-07-31 14:19 ` Alexandru Elisei
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