From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8B5C5C3DA5D for ; Fri, 19 Jul 2024 10:06:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=5WT+IycyQajlCrlFWMnU8zaRFpd2lLDAWJQIEalrhPo=; b=ntlahxmlnFb/za4aq5gKaU/xuu 839XY0078MNp2Xx3lbV4wphLQcHYBQv2xtS6RLYSfsR8KXxbtcNh+wMyfn+JyZAS9nP7LkLu6eOUq dGZSSJ6j9TjJ4T1GN92lhCgOu55RwcwzMi4zG6ZU1BkKnsY34FV6Gga9i9ob0xkBRcsvrnpIaVK/r EMrtMc8nog7jPDGiQfQARxAb01uw3jA7kAAlVnAATgeEPY0ON/7eN4AuQ7/EFv/wzbHkx9rXrUvua V90W75rm6SK74pi38hjdvtg+2Le0p2a/Ob1499ktmkLmrrbRphgIP5QtvB/bItpPdOHacMBpV1DZj u1rtzs3w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sUkUr-00000002MEt-11Fi; Fri, 19 Jul 2024 10:05:53 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sUkUU-00000002MD7-1g9h for linux-arm-kernel@lists.infradead.org; Fri, 19 Jul 2024 10:05:32 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 140D51063; Fri, 19 Jul 2024 03:05:53 -0700 (PDT) Received: from J2N7QTR9R3 (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0F8A73F762; Fri, 19 Jul 2024 03:05:26 -0700 (PDT) Date: Fri, 19 Jul 2024 11:05:21 +0100 From: Mark Rutland To: Luca Fancellu Cc: andre.przywara@arm.com, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 3/6] aarch64: Remove TSCXT bit set from SCTLR_EL2_RESET Message-ID: References: <20240716142906.1502802-1-luca.fancellu@arm.com> <20240716142906.1502802-4-luca.fancellu@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240716142906.1502802-4-luca.fancellu@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240719_030530_511529_4C48452B X-CRM114-Status: GOOD ( 18.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Jul 16, 2024 at 03:29:03PM +0100, Luca Fancellu wrote: > From the specification SCTLR_EL2.TSCXT is RES1 only "When > FEAT_CSV2_2 is not implemented, FEAT_CSV2_1p2 is not > implemented, HCR_EL2.E2H == 1 and HCR_EL2.TGE == 1", so > given that HCR_EL2.E2H is set by bootwrapper before to a > value of zero, the condition above can't happen and from > the specification the bit is RES0. > > Fix the macro removing the bit. > > Signed-off-by: Luca Fancellu > Reviewed-by: Andre Przywara Since this is a fix independenny of the rest of the series, I've applied this on its own and pushed it out. I'll chew through the rest of the series shortly. Mark. > --- > v2 changes: > - Add Andre R-by > --- > arch/aarch64/include/asm/cpu.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h > index 124ef916ddfc..846b89f8405d 100644 > --- a/arch/aarch64/include/asm/cpu.h > +++ b/arch/aarch64/include/asm/cpu.h > @@ -30,8 +30,8 @@ > BIT(11) | BIT(5) | BIT(4)) > > #define SCTLR_EL2_RES1 \ > - (BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(20) | BIT(18) | \ > - BIT(16) | BIT(11) | BIT(5) | BIT(4)) > + (BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(18) | BIT(16) | \ > + BIT(11) | BIT(5) | BIT(4)) > > #define SCTLR_EL1_RES1 \ > (BIT(29) | BIT(28) | BIT(23) | BIT(22) | BIT(20) | BIT(11) | \ > -- > 2.34.1 >