From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8A66DC3DA64 for ; Sun, 4 Aug 2024 13:22:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=GOehU5C/2N6ZqV5VxIDAQPJar3wdkYDxUaOyeXY8lQw=; b=i/7MSuZ2tR48jy9f9EDMPBh4TA A857twyYjEavcGvJv32M+HNSAYVDB9MxPBvlto9vJjPu1/qxb47+rTCyxcgWDDozWTDQ71/DWLVag qX5W0eYCs4aSaGI9b8YUZk9AB1TmZzW9RhMF6XNqHTU7blgZhi/k0JY1mHRHO/Iruem+TUp9uU7Iw /tC8ga0AV1LMG81W9+hjoqP9IqOXv7kxV08rk5mPZx9WjmQCab6nGAvCOpdy+DNdqvLqzgizRh07v OdAg4wYVZfZOMjzozAIYytEJPt3m7AgDox6QkZXfL/tWHwZx6KmBgpGOqE+JMEvjTpWC475qIr8gV dGyDA1JA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sabBE-0000000DJMk-1A9n; Sun, 04 Aug 2024 13:21:48 +0000 Received: from layka.disroot.org ([178.21.23.139]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1sabAg-0000000DJHg-2aC2; Sun, 04 Aug 2024 13:21:17 +0000 Received: from localhost (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 9A83141837; Sun, 4 Aug 2024 15:21:09 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3CTz3J9dJQ3A; Sun, 4 Aug 2024 15:21:08 +0200 (CEST) Date: Sun, 4 Aug 2024 21:20:21 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1722777668; bh=G/uPcnpBqI+s3ISHwUMI67Yv9MNHULgt9fA5st8EqjU=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=Vq5AYFEMExG7hVajp7HkalzaK5eYLARsqunAEv72vGryV1WDr9CX50jLSGAiJsMnX VrrsTf8BVDuqLcxvx9cnfOU/62EUJq+j5GDYTBUGS1AgNIC6ibsAscQuqPWX/SsG52 8vdiyxabi6EA2hnbCutQOns9hXKUcV9v7kj6LRxQND8dbiMEf/44Vuu+KvZmb1SCPY Z4I3un8+PtVM9X6uIXUITtnsZAZGXV7ExqPTqP5vLYJ5ak8ZZ1dQ6t02OprTD3K/Hi VKnrmh92d49yTxQigl5weFVQZXR6HOAh1oyD6Fh3zR+e5YhH4sdTyQWWEBOYilVXon vDuxn8/eFM33w== From: Yao Zi To: Krzysztof Kozlowski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Greg Kroah-Hartman , Jiri Slaby , Chris Morgan , Jonas Karlman , Tim Lunn , Andy Yan , Muhammed Efe Cetin , Jagan Teki , Dragan Simic , Ondrej Jirman Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org Subject: Re: [PATCH 3/4] arm64: dts: rockchip: Add base DT for rk3528 SoC Message-ID: References: <20240803125510.4699-2-ziyao@disroot.org> <20240803125510.4699-5-ziyao@disroot.org> <56bd1478-ce8c-4c1d-ab16-afe4ad462bf5@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <56bd1478-ce8c-4c1d-ab16-afe4ad462bf5@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240804_062115_246958_77E4A6A6 X-CRM114-Status: GOOD ( 23.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sun, Aug 04, 2024 at 12:05:11PM +0200, Krzysztof Kozlowski wrote: > On 03/08/2024 14:55, Yao Zi wrote: > > This initial device tree describes CPU, interrupts and UART on the chip > > and is able to boot into basic kernel with only UART. Cache information > > is omitted for now as there is no precise documentation. Support for > > other features will be added later. > > > > Signed-off-by: Yao Zi > > --- > > arch/arm64/boot/dts/rockchip/rk3528.dtsi | 182 +++++++++++++++++++++++ > > 1 file changed, 182 insertions(+) > > create mode 100644 arch/arm64/boot/dts/rockchip/rk3528.dtsi > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi > > new file mode 100644 > > index 000000000000..77687d9e7e80 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi > > @@ -0,0 +1,182 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > +/* > > + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. > > + * Copyright (c) 2024 Yao Zi > > + */ > > + > > +#include > > +#include > > + > > +/ { > > + compatible = "rockchip,rk3528"; > > + > > + interrupt-parent = <&gic>; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + aliases { > > + serial0 = &uart0; > > + serial1 = &uart1; > > + serial2 = &uart2; > > + serial3 = &uart3; > > + serial4 = &uart4; > > + serial5 = &uart5; > > + serial6 = &uart6; > > + serial7 = &uart7; > > + }; > > + > > + cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + cpu-map { > > + cluster0 { > > + core0 { > > + cpu = <&cpu0>; > > + }; > > + core1 { > > + cpu = <&cpu1>; > > + }; > > + core2 { > > + cpu = <&cpu2>; > > + }; > > + core3 { > > + cpu = <&cpu3>; > > + }; > > + }; > > + }; > > + > > + cpu0: cpu@0 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a53"; > > + reg = <0x0>; > > + enable-method = "psci"; > > + }; > > + > > + cpu1: cpu@1 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a53"; > > + reg = <0x1>; > > + enable-method = "psci"; > > + }; > > + > > + cpu2: cpu@2 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a53"; > > + reg = <0x2>; > > + enable-method = "psci"; > > + }; > > + > > + cpu3: cpu@3 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a53"; > > + reg = <0x3>; > > + enable-method = "psci"; > > + }; > > + }; > > + > > + psci { > > + compatible = "arm,psci-1.0", "arm,psci-0.2"; > > + method = "smc"; > > + }; > > + > > + timer { > > + compatible = "arm,armv8-timer"; > > + interrupts = , > > + , > > + , > > + ; > > + }; > > + > > + xin24m: xin24m { > > Please use name for all fixed clocks which matches current format > recommendation: 'clock-([0-9]+|[a-z0-9-]+)+' Will be fixed in next revision. > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/clock/fixed-clock.yaml?h=v6.11-rc1 > > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <24000000>; > > + clock-output-names = "xin24m"; > > + }; > > + > > + gic: interrupt-controller@fed01000 { > > Why this all is outside of SoC? Just as Heiko says, device tree for all other Rockchip SoCs don't have a "soc" node. I didn't know why before but just follow the style. If you prefer add a soc node, I am willing to. Best regards, Yao Zi