From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 87EFFC3DA4A for ; Sat, 3 Aug 2024 10:53:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=mu9FkY4c/uJVBGujkX9O9T3U1DDJPdfc+ijfF/DuS4c=; b=3HWmUktTPptS53KNJOWLqer2Nr k5+Ne4heEa8v9PQp2Awep0FElnPirfYI19hlCuMRbfs85YRikxKq3CSIYguNsV3bB6IvNIGCVN37P TvOBADVHMeBR5B9yKOOU6VmUsDoXNmJb8SeeB5PDca5833kcfgrLE+qrDMKwFJQ7f1Sf6pgQjdPSg YtsdgykBvq9u4M6HOwnzWtiQjIU3FN2dG/3OAl7XnTCGgn9tkiExJt4UjLBLdLmFmgPl/JHpukthR hnB0OJmDfzblGPp3v5LCjt+zT4QKvyyImUguCEnFq6AUOUQgDdgCLqsek78Dyy/2NWJn1iyVGAnOQ reb4FSHw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1saCOP-0000000BEW2-0az9; Sat, 03 Aug 2024 10:53:45 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1saCNt-0000000BEU1-1dVx for linux-arm-kernel@lists.infradead.org; Sat, 03 Aug 2024 10:53:14 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D5B17DA7; Sat, 3 Aug 2024 03:53:37 -0700 (PDT) Received: from J2N7QTR9R3 (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 40E9A3F64C; Sat, 3 Aug 2024 03:53:11 -0700 (PDT) Date: Sat, 3 Aug 2024 11:53:08 +0100 From: Mark Rutland To: Andre Przywara Cc: linux-arm-kernel@lists.infradead.org, akos.denke@arm.com, luca.fancellu@arm.com, maz@kernel.org Subject: Re: [BOOT-WRAPPER 01/11] Always enter AArch32 kernels in ARM mode Message-ID: References: <20240729161501.1806271-1-mark.rutland@arm.com> <20240729161501.1806271-2-mark.rutland@arm.com> <20240802122639.30aebecb@donnerap.manchester.arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240802122639.30aebecb@donnerap.manchester.arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240803_035313_555622_F3E9A10F X-CRM114-Status: GOOD ( 33.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Aug 02, 2024 at 12:26:39PM +0100, Andre Przywara wrote: > On Mon, 29 Jul 2024 17:14:51 +0100 > Mark Rutland wrote: > > > Currnetly we try to support entering AArch32 kernels, but this is > > I think you are missing "in Thumb mode" here? The read is a bit confusing > otherwise. > > > unnecessary, and the code is never exercised. > > > > Per Linux's Documentation/arch/arm/booting.txt, AArch32 kernels > > supported by the AArch64 boot-wrapper should always be entered in ARM > > mode: > > > > | The boot loader is expected to call the kernel image by jumping > > | directly to the first instruction of the kernel image. > > | > > | On CPUs supporting the ARM instruction set, the entry must be > > | made in ARM state, even for a Thumb-2 kernel. > > | > > | On CPUs supporting only the Thumb instruction set such as > > | Cortex-M class CPUs, the entry must be made in Thumb state. > > > > Additionally, the kernel__start symbol that we use as the kernel > > entrypoint is always PHYS_OFFSET + KERNEL_OFFSET, which doesn't take > > into account any ARM/Thumb distinction in the AArch32 kernel image, and > > hence we'll never try to set the Thumb bit in the SPSR. > > Is that true? I see the first_spin code path for CPU 0 using those values, > which indeed never have bit 0 set, but the address could come from *mbox > as well, given by the live kernel in the PSCI code path, and we don't have > any control over that. > Or do I miss anything here? You're right, and PSCI explicitly describes that bit 0 in the entry address results in the T bit being set in CPSR. I will drop this patch, and adjust subsequent paqtches accordingly. Mark. > I think the patch is still valid, but we might need to relax the commit > message here a bit? > > Cheers, > Andre > > > > > Remove the redundant code. > > > > Signed-off-by: Mark Rutland > > Cc: Akos Denke > > Cc: Andre Przywara > > Cc: Luca Fancellu > > Cc: Marc Zyngier > > --- > > arch/aarch32/boot.S | 4 ---- > > arch/aarch64/boot.S | 7 ------- > > 2 files changed, 11 deletions(-) > > > > diff --git a/arch/aarch32/boot.S b/arch/aarch32/boot.S > > index 4d16c9c..5c2a183 100644 > > --- a/arch/aarch32/boot.S > > +++ b/arch/aarch32/boot.S > > @@ -105,10 +105,6 @@ ASM_FUNC(jump_kernel) > > bxeq lr @ no EL3 > > > > ldr r4, =SPSR_KERNEL > > - /* Return in thumb2 mode when bit 0 of address is 1 */ > > - tst lr, #1 > > - orrne r4, #PSR_T > > - > > msr spsr_cxf, r4 > > movs pc, lr > > > > diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S > > index da5fa65..b889137 100644 > > --- a/arch/aarch64/boot.S > > +++ b/arch/aarch64/boot.S > > @@ -136,13 +136,6 @@ ASM_FUNC(jump_kernel) > > br x19 // No EL3 > > > > 1: mov x4, #SPSR_KERNEL > > - > > - /* > > - * If bit 0 of the kernel address is set, we're entering in AArch32 > > - * thumb mode. Set SPSR.T accordingly. > > - */ > > - bfi x4, x19, #5, #1 > > - > > msr elr_el3, x19 > > msr spsr_el3, x4 > > eret >