From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8CE43C3DA5D for ; Thu, 25 Jul 2024 08:41:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=apKOCkHqrNKO1v97N6ZNHgOVjVeW1fEwPu8M+mTu9/4=; b=moq41m202SHFre/t6G38XMaazY JgmHt+ajLJ97CKsDoI8Z+BG1vvquQ7JsglwFf72NrYjmt2tI4hz/i1ywDmp13cJuPXomzJKprMbzu D7tCGY29Ocncke1QUdPd7XTGpQVUUpFNftWUHmN31EE32SRjj1T8voTG+7IXl34x80Y/zCrS0jLIk gwm4yT7nVJkAqkvVjsTNjeqgwV43rlBhIic1dRhzJn8OVKvqT02O6efnMG+TJKPiv+UbDFb2+kZE4 BeNt6Wn07OWvUIrK8FTCCK8BaHQdXcSUFtkDIqQ1MLaQfzzDPNODW9/avyDa1OHWAd5T++MUjURao BsYG7zEg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sWu2C-00000000Mnf-3EYW; Thu, 25 Jul 2024 08:41:13 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sWu1o-00000000Mlj-2MXI for linux-arm-kernel@lists.infradead.org; Thu, 25 Jul 2024 08:40:50 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F00DA1007; Thu, 25 Jul 2024 01:41:11 -0700 (PDT) Received: from J2N7QTR9R3 (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E4E433F73F; Thu, 25 Jul 2024 01:40:45 -0700 (PDT) Date: Thu, 25 Jul 2024 09:40:39 +0100 From: Mark Rutland To: Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org Subject: Re: [boot-wrapper 2/3] aarch64: Enable access into SCTLR2_ELx registers from EL2 and below Message-ID: References: <20240723110630.483871-1-anshuman.khandual@arm.com> <20240723110630.483871-3-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240723110630.483871-3-anshuman.khandual@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240725_014048_678873_E1169290 X-CRM114-Status: GOOD ( 19.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Jul 23, 2024 at 04:36:29PM +0530, Anshuman Khandual wrote: > FEAT_SCTLR2 adds SCTLR2_EL1 and SCTLR2_EL2 system registers But access into > these register from EL2 and below trap to EL3 unless SCR_EL3.D128En is set. > > Enable access to SCTLR2_ELx registers when they are implemented. > > Signed-off-by: Anshuman Khandual I think this should be first in the series, since SCTLR2 can exist without D128, but not vice-versa. > --- > arch/aarch64/include/asm/cpu.h | 4 +++- > arch/aarch64/init.c | 3 +++ > 2 files changed, 6 insertions(+), 1 deletion(-) > > diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h > index 0b8b463..57d66e4 100644 > --- a/arch/aarch64/include/asm/cpu.h > +++ b/arch/aarch64/include/asm/cpu.h > @@ -56,6 +56,7 @@ > #define SCR_EL3_HXEn BIT(38) > #define SCR_EL3_EnTP2 BIT(41) > #define SCR_EL3_TCR2EN BIT(43) > +#define SCR_EL3_SCTLR2En BIT(44) > #define SCR_EL3_PIEN BIT(45) > #define SCR_EL3_D128En BIT(47) > > @@ -81,7 +82,8 @@ > > #define ID_AA64MMFR1_EL1_HCX BITS(43, 40) > > -#define ID_AA64MMFR3_EL1_TCRX BITS(4, 0) > +#define ID_AA64MMFR3_EL1_TCRX BITS(3, 0) > +#define ID_AA64MMFR3_EL1_SCTLRX BITS(7, 4) > #define ID_AA64MMFR3_EL1_S1PIE BITS(11, 8) > #define ID_AA64MMFR3_EL1_S2PIE BITS(15, 12) > #define ID_AA64MMFR3_EL1_S1POE BITS(19, 16) > diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c > index 7d9d0d9..5b21cb8 100644 > --- a/arch/aarch64/init.c > +++ b/arch/aarch64/init.c > @@ -92,6 +92,9 @@ void cpu_init_el3(void) > if (mrs_field(ID_AA64MMFR3_EL1, D128)) > scr |= SCR_EL3_D128En; > > + if (mrs_field(ID_AA64MMFR3_EL1, SCTLRX)) > + scr |= SCR_EL3_SCTLR2En; > + The SCTLR2_ELx registers reset to UNKNOWN values when the highest implemented exception level is not ELx, so we need to initialize those to safe values. Otherwise a kernel which is not aware of SCTLR2_ELx will be subject to arbitrary behaviour as a result of the SCTLR2_ELx bits which it will not have configured. I know that we've failed to do that for other things (FGT and HCRX), and those are latent bugs / mistakes in our appraoch that I'll see about fixing. Mark.