From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CA3C1C3DA5D for ; Thu, 25 Jul 2024 08:51:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=zErXemFpwKugRpVIK15XrfGK1rvKBMSB/JvYOVWnXD4=; b=Ppc2F5ItyiLyKZM+Tjc3z41kka JW9dM4d3BMq6PKIMTBRzfl2zc7qp8YDSE3eijE3a1N64qfV2q5eeYpIL+0QYC92mL330RI9pCJklc BhH6cmV+OAilMQDfLBRAPiJF7oqupsmNERQbtu2rBWYs4vzV/LS+888t6m/9VxkQxgZ1ecd20NE8s rl4Vq+XEUyiUhf2g2hgXCMrPqUTTcoJK35vdL8qfwsxajW5DIywVh+WUoqgPFb72JmRYOs2/u/hso 27TA3Ih4UELT+0Gqe+LIWnfheqbHc0ZJ5uS1OFuwXbs0TVc/W0I1Wjl/0fybHcoAsznkha2X4NOf6 9X3SD2qQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sWuC9-00000000O3N-2vVm; Thu, 25 Jul 2024 08:51:30 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sWuBl-00000000O0V-0oIK for linux-arm-kernel@lists.infradead.org; Thu, 25 Jul 2024 08:51:06 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6DEF91007; Thu, 25 Jul 2024 01:51:29 -0700 (PDT) Received: from J2N7QTR9R3 (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6B9423F5A1; Thu, 25 Jul 2024 01:51:03 -0700 (PDT) Date: Thu, 25 Jul 2024 09:51:01 +0100 From: Mark Rutland To: Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org Subject: Re: [boot-wrapper 3/3] aarch64: Enable access into RCW[S]MASK_EL1 registers from EL2 and below Message-ID: References: <20240723110630.483871-1-anshuman.khandual@arm.com> <20240723110630.483871-4-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240723110630.483871-4-anshuman.khandual@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240725_015105_292574_B1C89656 X-CRM114-Status: GOOD ( 16.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Jul 23, 2024 at 04:36:30PM +0530, Anshuman Khandual wrote: > FEAT_THE adds RCW[S]MASK_EL1 system registers. But access into these system > registers from EL2 and below trap to EL3 unless SCR_EL3.RCWMASKEn is set. > > Enable access to RCW[S]MASK_EL1 registers when they are implemented. This looks fine. IIUC we don't need to initialize these new registers as they only affect the behaviour of new instructions which we don't expect SW to use until privileged SW has configured these registers (as they reset to UNKNOWN values even at the highest implemented EL). Mark. > Signed-off-by: Anshuman Khandual > --- > arch/aarch64/include/asm/cpu.h | 2 ++ > arch/aarch64/init.c | 3 +++ > 2 files changed, 5 insertions(+) > > diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h > index 57d66e4..8404152 100644 > --- a/arch/aarch64/include/asm/cpu.h > +++ b/arch/aarch64/include/asm/cpu.h > @@ -55,6 +55,7 @@ > #define SCR_EL3_TME BIT(34) > #define SCR_EL3_HXEn BIT(38) > #define SCR_EL3_EnTP2 BIT(41) > +#define SCR_EL3_RCWMASKEn BIT(42) > #define SCR_EL3_TCR2EN BIT(43) > #define SCR_EL3_SCTLR2En BIT(44) > #define SCR_EL3_PIEN BIT(45) > @@ -92,6 +93,7 @@ > > #define ID_AA64PFR1_EL1_MTE BITS(11, 8) > #define ID_AA64PFR1_EL1_SME BITS(27, 24) > +#define ID_AA64PFR1_EL1_THE BITS(51, 48) > #define ID_AA64PFR0_EL1_SVE BITS(35, 32) > > #define ID_AA64SMFR0_EL1 s3_0_c0_c4_5 > diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c > index 5b21cb8..13a2339 100644 > --- a/arch/aarch64/init.c > +++ b/arch/aarch64/init.c > @@ -95,6 +95,9 @@ void cpu_init_el3(void) > if (mrs_field(ID_AA64MMFR3_EL1, SCTLRX)) > scr |= SCR_EL3_SCTLR2En; > > + if (mrs_field(ID_AA64PFR1_EL1, THE)) > + scr |= SCR_EL3_RCWMASKEn; > + > msr(SCR_EL3, scr); > > msr(CPTR_EL3, cptr); > -- > 2.25.1 >