From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C21F1C3DA49 for ; Fri, 26 Jul 2024 08:45:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=GONgbF/nD40LudTvR8Ynt7FHJ9IEgWJ/M3bCW2LtX0s=; b=AOwhebVbR2tqVmIMhGHBJ/kr3h dmGRX2Kh84sJy/o4Z/mQH6OcUtjvIAQEw2vO8xn9daXDrPwoo9nX9a2mzVZMCvgOv4oxZVzztn9DH A8yUirJvqLxirYPJe4xY1bQk7gBol1mJ12WBBMXmt8LEQrjbXqKhZqLHFWKGaSQY0ET78f7RAofq0 85/HLFgc2MzVgCxHnp/Kw3rbKhTOLOa4ZV6Ob8jm3E0qMpa1Q071IlNkokOoOvWkpvHAToE+umLaN DPJP9qTv/DOcK0wBz7jG15BlX8jL+hTOOMT3IJ5azicvssAoY/qRgHjeizmMQ5LMx3RQ2dGUdDKb5 65y0EhLA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sXGa6-00000003MKf-3Kz6; Fri, 26 Jul 2024 08:45:42 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sXGZg-00000003MDl-2Az6 for linux-arm-kernel@lists.infradead.org; Fri, 26 Jul 2024 08:45:18 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 779F11007; Fri, 26 Jul 2024 01:45:38 -0700 (PDT) Received: from J2N7QTR9R3.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 671C33F5A1; Fri, 26 Jul 2024 01:45:12 -0700 (PDT) Date: Fri, 26 Jul 2024 09:45:02 +0100 From: Mark Rutland To: Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org Subject: Re: [boot-wrapper 2/3] aarch64: Enable access into SCTLR2_ELx registers from EL2 and below Message-ID: References: <20240723110630.483871-1-anshuman.khandual@arm.com> <20240723110630.483871-3-anshuman.khandual@arm.com> <498bab5b-010c-4505-b081-5570c33d4d33@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <498bab5b-010c-4505-b081-5570c33d4d33@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240726_014517_113896_3C6611EB X-CRM114-Status: GOOD ( 23.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jul 26, 2024 at 12:25:14PM +0530, Anshuman Khandual wrote: > On 7/25/24 14:10, Mark Rutland wrote: > > On Tue, Jul 23, 2024 at 04:36:29PM +0530, Anshuman Khandual wrote: > >> diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c > >> index 7d9d0d9..5b21cb8 100644 > >> --- a/arch/aarch64/init.c > >> +++ b/arch/aarch64/init.c > >> @@ -92,6 +92,9 @@ void cpu_init_el3(void) > >> if (mrs_field(ID_AA64MMFR3_EL1, D128)) > >> scr |= SCR_EL3_D128En; > >> > >> + if (mrs_field(ID_AA64MMFR3_EL1, SCTLRX)) > >> + scr |= SCR_EL3_SCTLR2En; > >> + > > > > The SCTLR2_ELx registers reset to UNKNOWN values when the highest > > implemented exception level is not ELx, so we need to initialize those > > to safe values. Otherwise a kernel which is not aware of SCTLR2_ELx will > > be subject to arbitrary behaviour as a result of the SCTLR2_ELx bits > > which it will not have configured. > > Both SCTLR2_EL1 and SCTLR2_EL2 has the same register fields layout > except the very last bit i.e SCTLR2_EL2.EMEC which is available in > SCTLR2_EL2 but not in SCTLR2_EL1. > > AFAICT all the above register fields are applicable for newer arch > features which the current kernel is not even aware about. So even > if the kernel is not ware about SCTLR2_EL2 or SCTLR2_EL1 registers, > there will not be any difference in behaviour related to these new > arch features. There several are changes to existing behaviours. Looking at ARM DDI 0487K.a: * EASE changes the way external aborts are routed, which could surprise the exception handling code. * NMEA causes SError to be taken regardless of PSTATE.A. This *will* break exception handling. ... and regardless we have no idea how any of the RES0 bits will be used in future. Looking at DDI 0601 ID070124 from: https://developer.arm.com/documentation/ddi0601/2024-06/?lang=en ... there are other bits that would be problematic too. Consider how EnPACM0 works with a kernel that is not PACM-aware but a userspace that is, especially if CPUs have mismatched reset values. > Search for the registers in the current mainline kernel. > > $git grep SCTLR2_EL > > arch/arm64/include/asm/sysreg.h:#define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3) > arch/arm64/include/asm/sysreg.h:#define SYS_SCTLR2_EL12 sys_reg(3, 5, 1, 0, 3) > arch/arm64/kvm/emulate-nested.c: SR_TRAP(SYS_SCTLR2_EL2, CGT_HCR_NV), > > $git grep SCTLR2En > arch/arm64/kvm/nested.c: res0 |= HCRX_EL2_SCTLR2En; > arch/arm64/tools/sysreg:Field 15 SCTLR2En > > Although if we are looking for safer values, guess resetting these > two registers might be sufficient here ? > > + if (mrs_field(ID_AA64MMFR3_EL1, SCTLRX)) { > + scr |= SCR_EL3_SCTLR2En; > + msr(SCTLR2_EL2, 0); > + msr(SCTLR2_EL1, 0); > + } Using zero for both looks fine to me. Mark.