From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CD565C3DA4A for ; Mon, 29 Jul 2024 13:31:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ctpW18F/RzB3MGHu3LJeLam3FIhE9FpoJQLY5xr/RVo=; b=pifzwCNeeCFn6w88n3tu+NeSj1 n1CwzvxhL4H5EwSPBp4fDPV/2/UDb3V+ds/yfQS5aZm1WHngsQIZuejvUmYsCo1HuihRM8+lBh845 znTlFJ927vlPAvvV5O37ZIQYLTq8O93M/GOnM4WJOn3S+49rnK6fqc2ELNl1A8WZ7U+IdAMCD5isF qzLmoXf06Zoa+4kE+nwxfRLeZpKoTZJf2H/Pk4GzeMr3zHCEMdtFPKb/3OKNNKQDaSHzJAuRUwl+K tWclAW1lij4P01Vy7FvmHT/5Za13QtOmEthfGeZ2/G39GVl2qWwyRygEGRas4/0NqJSh6Uj2Im/cl TquxeJtg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYQSm-0000000BR5o-3wTz; Mon, 29 Jul 2024 13:30:56 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sYQRv-0000000BQtV-3Dpg for linux-arm-kernel@lists.infradead.org; Mon, 29 Jul 2024 13:30:06 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DDD201007; Mon, 29 Jul 2024 06:30:27 -0700 (PDT) Received: from J2N7QTR9R3 (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C62893F766; Mon, 29 Jul 2024 06:30:01 -0700 (PDT) Date: Mon, 29 Jul 2024 14:29:52 +0100 From: Mark Rutland To: Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH V2 0/3] aarch64: Enable access for FEAT_D128 registers in EL1/EL2 Message-ID: References: <20240729043606.871451-1-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240729043606.871451-1-anshuman.khandual@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240729_063003_882546_6778A31E X-CRM114-Status: GOOD ( 12.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jul 29, 2024 at 10:06:03AM +0530, Anshuman Khandual wrote: > This series enables access for FEAT_D128 relevant registers in EL1/EL2 via > setting respective bits in SCR_EL3, when their corresponding features are > detected. > > -------------------------------------------------------------- > | FEAT_D128 | ID_AA64MMFR3_EL1_D128 | SCR_EL3_D128En | > | FEAT_SCTLR2 | ID_AA64MMFR3_EL1_SCTLRX | SCR_EL3_SCTLR2En | > | FEAT_THE | ID_AA64PFR1_EL1_THE | SCR_EL3_RCWMASKEn | > -------------------------------------------------------------- > > Changes in V2: > > - Moved up the patch related to SCTLR2_ELx from [PATCH 2/3] to [PATCH 1/3] > - Updated the commit message for the above mentioned patch > - Fixed the commit message s/D128En/SCTLR2En as the enabling bit > - Reset SCTLR2_ELx registers so that unaware kernels do not get surprises > > Changes in V1: > > https://lore.kernel.org/all/20240723110630.483871-1-anshuman.khandual@arm.com/ > > Anshuman Khandual (3): > aarch64: Enable access into SCTLR2_ELx registers from EL2 and below > aarch64: Enable access into 128 bit system registers from EL2 and below > aarch64: Enable access into RCW[S]MASK_EL1 registers from EL2 and below Thanks; applied. Mark.