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Fri, 16 Aug 2024 12:42:19 -0700 Date: Fri, 16 Aug 2024 12:42:17 -0700 From: Nicolin Chen To: Will Deacon CC: , , , , , , , , , Subject: Re: [PATCH v11 9/9] iommu/tegra241-cmdqv: Limit CMDs for guest owned VINTF Message-ID: References: <153fb887cf4bf6318c6f313a4be9b40a25a24e7d.1722993435.git.nicolinc@nvidia.com> <20240816132103.GA24411@willie-the-truck> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D7:EE_|LV8PR12MB9269:EE_ X-MS-Office365-Filtering-Correlation-Id: 80a28f0f-87f5-4596-200a-08dcbe2b9688 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?CBDJSyBlFyk7S/HvZ6viWfj0ao1HaFa6JFHr6egB86vxPRJh9olfvq6O7Mij?= =?us-ascii?Q?Z+8+PiJkPUQ8jsXiV7vn03LSZnD3lIRfjrjDZNRhFRdM1yUjnmkqRKqBoIFv?= =?us-ascii?Q?9fags8rQDwS67gRfcm1EPersneFGZnpNC5kVGcIAX1RK74gTGVUWPxTPlUBT?= =?us-ascii?Q?S4zCObI4rmkqcvDQ8kUcAC/8Gzhx9byPSklTIxB1Z9Ve9lFSt0BSAYQsAPhw?= =?us-ascii?Q?9/NkBkqaF/tM6SY+/6Ns0+lmh9xhWLNsdhnE89Y3wQWQzmUce/PBSjZlPDkC?= =?us-ascii?Q?uUAYlSNU9uchv3+p4P+pPtNC1eBpN1N5Ai8rBHni8D0rfW352PyqHtMEpSNY?= =?us-ascii?Q?c4xjj1onEiwETRI40zNbUfpLI/6+7idZx4pJysYLx4PKpPBOrsT9xtUmn8gE?= =?us-ascii?Q?4XOP7SjRyXAEyyIXXnrYIP88K+CBEpsixkwxGmWcAkNIAbdqcDeEPBU6L8h9?= =?us-ascii?Q?GE1DmbfJbme73zVQlb8sMgE7P8Wy3UA05EJCaHpv/jV/Y6pdm/e0ctO6RMoF?= =?us-ascii?Q?/fcspcSU8R3mdzpWXPncrrKtO20VDHg1uyu/+ROPQ6syBbBEhF3QuHrACMTV?= =?us-ascii?Q?PtQt/uDHBQVKnd4kTjiuGM/kn5mbPvh8Ip7hoXLFEwYs9eDvAaU7AXTpwZIl?= =?us-ascii?Q?2Hy9Yqu3aVm9gnkocAHTbcj+Hph/n78B6DxMY+lILRGA5JH7AztT6vCjdiV2?= =?us-ascii?Q?TRioK22H05zoFREQXdzwryzLls6atGnhFmHDgPGMLjz+fU2yoXKc+WZAH7mO?= =?us-ascii?Q?e2DpyIjcNq+HsaDrSbWGeIrUuQCPjUgJKmWeI+momxYPRi+k9j+GdKhnVy8h?= =?us-ascii?Q?PpdhnKJgx578FRvSkPEiRCvsjPLhhM9ph2TJZd3UPpHQjzjrlCAWQotvhCMb?= =?us-ascii?Q?7q5+Uv/wu3YZzwX0vTJld4r+YcGVtwm/fFVftmcHHsExCkrq0zfpa4gyerF8?= =?us-ascii?Q?CtMJVl5bH3HljboyJDLmAqWgBhQN5OHSto71zSRLF0iHaMFoBE5Rf34dJ2k3?= =?us-ascii?Q?sMxCVkOtIqmvAfBwtrnEADe/rpHVyavxLD5wxKUM094yBw4thGYI9xORNbxB?= =?us-ascii?Q?n1Cb21mJsTM3Cvb9SHEckdrlGwhqE76yZf9sLqb4sVjWXBNA1hEJLEF8zXgh?= =?us-ascii?Q?ILlCwjRGwY/6edr7MWVX1FkZopzPKtels3QmpkxFyCOEtaT1Xp6aUVwyXJvd?= =?us-ascii?Q?WFtFU1b2Bz8brPVRdw5GS94z2viv1hrr17X30sF0Dr31N6FVnbYOyU8Fd2fO?= =?us-ascii?Q?/yQv5pLa2xpjYeI7vZH4bhvEutNwP8V1ArWCYwSMRyd3oJZ+b9AR7lDMg/aq?= =?us-ascii?Q?WigWCtbyuT2msO6EbvArrN7eQAwWhWmfaCO+q9Hd7LYUvpwIUdWyyelBYclF?= =?us-ascii?Q?pNN9AyBctXZy76El434JCUHQVvNEFe/y53zEfG2UxdVdEiDZkbQsu/x2LY/2?= =?us-ascii?Q?jWLZvulUM8qWM01rnVJ9J5bvdH4exY5g?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Aug 2024 19:42:39.6423 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 80a28f0f-87f5-4596-200a-08dcbe2b9688 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D7.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9269 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240816_124259_752732_EFAF1004 X-CRM114-Status: GOOD ( 26.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Aug 16, 2024 at 11:15:31AM -0700, Nicolin Chen wrote: > On Fri, Aug 16, 2024 at 10:34:24AM -0700, Nicolin Chen wrote: > > On Fri, Aug 16, 2024 at 02:21:03PM +0100, Will Deacon wrote: > > > > > > static void arm_smmu_cmdq_batch_init(struct arm_smmu_device *smmu, > > > > - struct arm_smmu_cmdq_batch *cmds) > > > > + struct arm_smmu_cmdq_batch *cmds, > > > > + u8 opcode) > > > > { > > > > + WARN_ON_ONCE(!opcode); > > > > > > This seems like a fairly arbitrary warning. Remove it? > > > > OK. > > > > > > + > > > > cmds->num = 0; > > > > - cmds->cmdq = arm_smmu_get_cmdq(smmu); > > > > + cmds->cmdq = arm_smmu_get_cmdq(smmu, opcode); > > > > > > If we stashed the opcode here, we could actually just enforce that all > > > commands in the batch are the same type in arm_smmu_cmdq_batch_add(). > > > > > > Would that work better for you or not? > > > > A guested-owned queue is okay to mix different command types: > > CMDQ_OP_TLBI_NH_ASID > > CMDQ_OP_TLBI_NH_VA > > CMDQ_OP_ATC_INV > > > > So, limiting a batch to one single opcode isn't ideal. Instead, > > if we really have to apply an enforcement to every batch_add(), > > I think the cmdq structure would need a scan function pointer: > > > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > index d0d7c75c030a..1a83ad5ebadc 100644 > > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > > @@ -918,2 +918,10 @@ static void arm_smmu_cmdq_batch_init(struct arm_smmu_device *smmu, > > > > +static bool arm_smmu_cmdq_supports_cmd(struct arm_smmu_cmdq *cmdq, > > + struct arm_smmu_cmdq_ent *ent) > > +{ > > + if (!cmdq->supports_cmd) > > + return true; > > + return cmdq->supports_cmd(ent); > > +} > > + > > static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu, > > @@ -924,4 +932,5 @@ static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu, > > > > - if (cmds->num == CMDQ_BATCH_ENTRIES - 1 && > > - (smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC)) { > > + if ((cmds->num == CMDQ_BATCH_ENTRIES - 1 && > > + (smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC)) || > > + !arm_smmu_cmdq_supports_cmd(cmds->cmdq, cmd)) { > > arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, > > We'd need re-init the batch after this too.. > > Nicolin > > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > > index e131d8170b90..c4872af6232c 100644 > > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > > @@ -616,2 +616,3 @@ struct arm_smmu_cmdq { > > atomic_t lock; > > + bool (*supports_cmd)(struct arm_smmu_cmdq_ent *ent); > > }; > > > > That being said, the whole thing doesn't seem to have a lot value > > at this moment, since the SMMU driver doesn't mix commands? OK. I have added a patch for this. Let's just make things a bit perfect at once. Here is a v13 branch that addressed most of your remarks here: https://github.com/nicolinc/iommufd/commits/vcmdq_in_kernel-v13 Would you please let me know if you are okay with this? Thank you Nicolin