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[104.199.75.203]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-429ded287d0sm48228805e9.12.2024.08.15.05.26.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Aug 2024 05:26:50 -0700 (PDT) Date: Thu, 15 Aug 2024 12:26:46 +0000 From: Mostafa Saleh To: Robin Murphy Cc: Jason Gunthorpe , linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, will@kernel.org, joro@8bytes.org, jean-philippe@linaro.org, nicolinc@nvidia.com, mshavit@google.com Subject: Re: [PATCH v2] iommu/arm-smmu-v3: Match Stall behaviour for S2 Message-ID: References: <20240814145633.2565126-1-smostafa@google.com> <20240814155151.GB3468552@ziepe.ca> <91d6574d-c67e-484c-ad96-91c9fd3d0c43@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <91d6574d-c67e-484c-ad96-91c9fd3d0c43@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240815_052652_669762_3BA2D4CD X-CRM114-Status: GOOD ( 24.95 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Robin, On Thu, Aug 15, 2024 at 01:16:19PM +0100, Robin Murphy wrote: > On 15/08/2024 12:30 pm, Mostafa Saleh wrote: > > Hi Jason, > > > > On Wed, Aug 14, 2024 at 12:51:51PM -0300, Jason Gunthorpe wrote: > > > On Wed, Aug 14, 2024 at 02:56:33PM +0000, Mostafa Saleh wrote: > > > > > > > Also described in the pseudocode “SteIllegal()” > > > > if eff_idr0_stall_model == '10' && STE.S2S == '0' then > > > > // stall_model forcing stall, but S2S == 0 > > > > return TRUE; > > > > > > This clips out an important bit: > > > > > > if STE.Config == '11x' then > > > [..] > > > if eff_idr0_stall_model == '10' && STE.S2S == '0' then > > > // stall_model forcing stall, but S2S == 0 > > > return TRUE; > > > > > > And here we are using STRTAB_STE_0_CFG_S1_TRANS which is 101 and won't > > > match the STE.Config qualification. > > > > > > The plain text language said the S2S is only required if the S2 is > > > translating, STRTAB_STE_0_CFG_S1_TRANS puts it in bypass. > > > > Yes, my bad, this should be for stage-2 only which is populated in > > arm_smmu_make_s2_domain_ste() > > > > > > > > > + /* > > > > + * S2S is ignored if stage-2 exists but not enabled. > > > > + * S2S is not compatible with ATS. > > > > + */ > > > > + if (master->stall_enabled && !ats_enabled && > > > > + smmu->features & ARM_SMMU_FEAT_TRANS_S2) > > > > + target->data[2] |= STRTAB_STE_2_S2S; > > > > > > We can't ignore ATS if it was requested here. > > I don't see much value in adding effectively-dead checks for something which > is already forbidden by the architecture. The definition of STALL_MODEL > explicitly states: > > "An SMMU associated with a PCI system must not have STALL_MODEL == 0b10". > Ah, I was expecting that as otherwise it's contradiction, but couldn't find it while searching. Thanks for pointing it out, I will drop all references to ATS then. Thanks, Mostafa > Thanks, > Robin.