From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B66B1C52D7D for ; Tue, 13 Aug 2024 09:18:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=9/LIllVTmRHtA1q8xb16WiqcX3MfJ5M4Nnx7n9PNoIQ=; b=mV6uwHbmzjMaakSeex9/T5AkNI p8HPYv/5NaBdh1WthwDWsPKY0scbUQs+owCiRFuMEIDZbeZd9prBZIMcu/k/T8kfjxbS3JEgB2Av9 EO7T1t52qc5zqi+T9rcLVZM7Z6y/pn57MvNrLSJ7cVLnBYwT6JfpSJ26xCY8qHqwBym0/RLlEm3MM X5H0tecqd+ikoWMv5G1ltEwQF8liUMMBnj4wbWGrb3iKOAA3weXJPYyx9C5YYNDjCW1KdXvKhd/Ih 0GROYWBvlafB+pTiRK4aXQqu4w+Bemgnc3T7RrxMjqoqa8wXCgAdhl36SoZ9vIl019XN4TCs+yp25 Dwji8Alg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sdnfR-000000037AL-0VjD; Tue, 13 Aug 2024 09:18:13 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sdnem-000000036uL-19OB for linux-arm-kernel@lists.infradead.org; Tue, 13 Aug 2024 09:17:33 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0B9C212FC; Tue, 13 Aug 2024 02:17:57 -0700 (PDT) Received: from raptor (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3BCAA3F73B; Tue, 13 Aug 2024 02:17:29 -0700 (PDT) Date: Tue, 13 Aug 2024 10:17:26 +0100 From: Alexandru Elisei To: Marc Zyngier Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Joey Gouly , Anshuman Khandual , Przemyslaw Gaj Subject: Re: [PATCH v2 13/17] KVM: arm64: nv: Add SW walker for AT S1 emulation Message-ID: References: <20240731194030.1991237-1-maz@kernel.org> <20240731194030.1991237-14-maz@kernel.org> <867cco1y4w.wl-maz@kernel.org> <8634n91v3z.wl-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <8634n91v3z.wl-maz@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240813_021732_401580_DDCD7AEA X-CRM114-Status: GOOD ( 28.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marc, On Mon, Aug 12, 2024 at 06:58:24PM +0100, Marc Zyngier wrote: > Hi Alex, > > On Mon, 12 Aug 2024 16:11:02 +0100, > Alexandru Elisei wrote: > > > > Hi Marc, > > > > On Sat, Aug 10, 2024 at 11:16:15AM +0100, Marc Zyngier wrote: > > > Hi Alex, > > > > > > @@ -136,12 +137,22 @@ static int setup_s1_walk(struct kvm_vcpu *vcpu, u32 op, struct s1_walk_info *wi, > > > va = (u64)sign_extend64(va, 55); > > > > > > /* Let's put the MMU disabled case aside immediately */ > > > - if (!(sctlr & SCTLR_ELx_M) || > > > - (__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_DC)) { > > > + switch (wi->regime) { > > > + case TR_EL10: > > > + if (__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_DC) > > > + wr->level = S1_MMU_DISABLED; > > > > In compute_translation_regime(), for AT instructions other than AT S1E2*, when > > {E2H,TGE} = {0,1}, regime is Regime_EL10. As far as I can tell, when regime is > > Regime_EL10 and TGE is set, stage 1 is disabled, according to > > AArch64.S1Enabled() and the decription of the TGE bit. > > Grmbl... I really dislike E2H=0. May it die a painful death. How about > this on top? > > diff --git a/arch/arm64/kvm/at.c b/arch/arm64/kvm/at.c > index 10017d990bc3..870e77266f80 100644 > --- a/arch/arm64/kvm/at.c > +++ b/arch/arm64/kvm/at.c > @@ -139,7 +139,19 @@ static int setup_s1_walk(struct kvm_vcpu *vcpu, u32 op, struct s1_walk_info *wi, > /* Let's put the MMU disabled case aside immediately */ > switch (wi->regime) { > case TR_EL10: > - if (__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_DC) > + /* > + * If dealing with the EL1&0 translation regime, 3 things > + * can disable the S1 translation: > + * > + * - HCR_EL2.DC = 0 > + * - HCR_EL2.{E2H,TGE} = {0,1} > + * - SCTLR_EL1.M = 0 > + * > + * The TGE part is interesting. If we have decided that this > + * is EL1&0, then it means that either {E2H,TGE} == {1,0} or > + * {0,x}, and we only need to test for TGE == 1. > + */ > + if (__vcpu_sys_reg(vcpu, HCR_EL2) & (HCR_DC | HCR_TGE)) > wr->level = S1_MMU_DISABLED; The condition looks good now. > fallthrough; > case TR_EL2: > > [...] > > > > > switch (desc & GENMASK_ULL(1, 0)) { > > case 0b00: > > case 0b10: > > goto transfault; > > case 0b01: > > /* Block mapping */ > > break; > > default: > > if (level == 3) > > break; > > } > > > > Is this better? Perhaps slightly easier to match against the descriptor layouts, > > but I'm not sure it's an improvement over your suggestion. Up to you, no point > > in bikeshedding over it. > > I think I'll leave it as is for now. I'm getting sick of this code... Agreed! Thanks, Alex