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Tue, 27 Aug 2024 14:23:08 -0700 Date: Tue, 27 Aug 2024 14:23:07 -0700 From: Nicolin Chen To: Jason Gunthorpe CC: , Hanjun Guo , , Joerg Roedel , Kevin Tian , , Len Brown , , , "Lorenzo Pieralisi" , "Rafael J. Wysocki" , Robert Moore , Robin Murphy , Sudeep Holla , Will Deacon , "Alex Williamson" , Eric Auger , Jean-Philippe Brucker , Moritz Fischer , Michael Shavit , , Shameerali Kolothum Thodi , Mostafa Saleh Subject: Re: [PATCH v2 8/8] iommu/arm-smmu-v3: Support IOMMU_DOMAIN_NESTED Message-ID: References: <0-v2-621370057090+91fec-smmuv3_nesting_jgg@nvidia.com> <8-v2-621370057090+91fec-smmuv3_nesting_jgg@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <8-v2-621370057090+91fec-smmuv3_nesting_jgg@nvidia.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D5:EE_|SJ0PR12MB8166:EE_ X-MS-Office365-Filtering-Correlation-Id: cf3918e4-8eab-4fa6-da96-08dcc6de79e5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|1800799024|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?NWX6stM1pw7GUa0ElGwOwjG/aZAQ8+Idu7m6mYUdJAxqY0cwcm9E3HIm0yKd?= =?us-ascii?Q?tf9HM2CGwXBGyi2vGV9SjgnOtwyUwoW3d5Q3DbVjCICNMsruIna08+YnGnLG?= =?us-ascii?Q?JRRtA+glOmlZMBhsj6GdWB9WRG16XVmgKzqTlF0GFza0NbiLrpAMnESGunGq?= =?us-ascii?Q?VTgv5XyuQwZrWBlySu57OdLD+PMmc9hlh4L37salcf0PAWDV48PYW/prFoZm?= =?us-ascii?Q?rTTmvoLusdzCEMDSnZac0pbWsoiSyCod2zdnv4DlBFgZ0L++InW6XJ1GY0n/?= =?us-ascii?Q?2nRTlI20dBkzmdZppO8R3D/JUReV8YoRx3V7tpvXyPlipwvuiuAdZnLrssxB?= =?us-ascii?Q?r9emHnxrRRROxGaxe/W9mRZvIqgtc0RNoUZ+vFzP1+i+cQwoFHcyAMllCB+f?= =?us-ascii?Q?CuuYpYqkCgexNxvZc8wYllUA5MYPezpS3XrnegXDVEYTOulTjDOdoiFZWP23?= =?us-ascii?Q?VleskrE8WbRPgMMwHWUWSOLb/LhvA/myLoqVrrTrzn3i20mPs8u71RWTWeCJ?= =?us-ascii?Q?ftR55jM7/KaN9HjrPWzOb7CYG0w8DqE/fw0qDWiXufZChRsod2qYWZhbnJW3?= =?us-ascii?Q?eqY5xl16NGmBmvSfB7keTijXf94Z/v1Nh2b07u6eyi0noS96BxeA4vNpmhMZ?= =?us-ascii?Q?pERaMVs7GQlgXRSMgUXCiCkvY13eFo6GBOMC6RnJkCJTaleuD24rTr/s6NOt?= =?us-ascii?Q?qWE8/lBQmO/+3lqXLwVJwimo8lvJXYuaZw0ksUKYvC+az9yw3ZwYmcgfJyGT?= =?us-ascii?Q?dXTbXKz2wv1gZXrzIzHMBaUZUWBDRNYE3VUTdi8KVLrat8Jlb+8gz2a01oLs?= =?us-ascii?Q?+a6dm7LwGJ6JE6TWdf9oRrtQl0phodp+EQXAW5MaQNEf7Dy4zcdoDzULfStc?= =?us-ascii?Q?sxapRnLesHU1EFzpKmuPX0QkQrCWME/sdjhopf5+YLsw+71cKGYsN8rOUed4?= =?us-ascii?Q?HapAByPL2dP2O1t436u1pb/kVcq2gaM5HWJmTo2LGLBQv92ohCfmo86C20TD?= =?us-ascii?Q?PETn/wm2BDPyW95/vMr8/OsQ3PhRlHlQojwP4I5lrwC67VNfqTdxfpBWewZB?= =?us-ascii?Q?1pVLP1nZOio5+VLFzhobR9iopteoLLY/oqz35QnRLYr0QdeWin/ZIRk17uib?= =?us-ascii?Q?d1Bf89vdh2rJ2cPI2I6s+VLMZPk46PSW3z4XM8su19UOVEtXl4BHgoiR0l6x?= =?us-ascii?Q?c+hUNjduqhxgBjVbrQH9XAJnxSl6UCIUlcLvVJk/FMxyX5ZEg3uJRA30Emvq?= =?us-ascii?Q?CbWIMZs0XiuPxiI/I9igBfSfdov0Iv1nmWiVYBSBjfnC3jCgGRrsR+ZdWYeq?= =?us-ascii?Q?mqbKT47xAmFpnadDhspOVMMDI+M9zUvA2azUXOSyxOwPkZcyhFsEwxGL52vK?= =?us-ascii?Q?OdE611b/fjNm2v7qVZQ3w2yrJnykLAoUykkXp3SNFk9wsW7843uM5iX9GKfm?= =?us-ascii?Q?g7uJBX4TyuKUVaiW7xCFldiHT5s56ubf?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(1800799024)(7416014)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Aug 2024 21:23:20.8820 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cf3918e4-8eab-4fa6-da96-08dcc6de79e5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB8166 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240827_142329_996531_9F1BA081 X-CRM114-Status: GOOD ( 28.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Aug 27, 2024 at 12:51:38PM -0300, Jason Gunthorpe wrote: > For SMMUv3 a IOMMU_DOMAIN_NESTED is composed of a S2 iommu_domain acting > as the parent and a user provided STE fragment that defines the CD table > and related data with addresses translated by the S2 iommu_domain. > > The kernel only permits userspace to control certain allowed bits of the > STE that are safe for user/guest control. > > IOTLB maintenance is a bit subtle here, the S1 implicitly includes the S2 > translation, but there is no way of knowing which S1 entries refer to a > range of S2. > > For the IOTLB we follow ARM's guidance and issue a CMDQ_OP_TLBI_NH_ALL to > flush all ASIDs from the VMID after flushing the S2 on any change to the > S2. > > Similarly we have to flush the entire ATC if the S2 is changed. > > Signed-off-by: Jason Gunthorpe Reviewed-by: Nicolin Chen With some small nits: > @@ -2192,6 +2255,16 @@ static void arm_smmu_tlb_inv_range_domain(unsigned long iova, size_t size, > } > __arm_smmu_tlb_inv_range(&cmd, iova, size, granule, smmu_domain); > > + if (smmu_domain->stage == ARM_SMMU_DOMAIN_S2 && > + smmu_domain->nest_parent) { smmu_domain->nest_parent alone is enough? [---] > +static int arm_smmu_attach_dev_nested(struct iommu_domain *domain, > + struct device *dev) > +{ [..] > + if (arm_smmu_ssids_in_use(&master->cd_table) || This feels more like a -EBUSY as it would be unlikely able to attach to a different nested domain? > + nested_domain->s2_parent->smmu != master->smmu) > + return -EINVAL; [---] > +static struct iommu_domain * > +arm_smmu_domain_alloc_nesting(struct device *dev, u32 flags, > + struct iommu_domain *parent, > + const struct iommu_user_data *user_data) > +{ > + struct arm_smmu_master *master = dev_iommu_priv_get(dev); > + struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); > + struct arm_smmu_nested_domain *nested_domain; > + struct arm_smmu_domain *smmu_parent; > + struct iommu_hwpt_arm_smmuv3 arg; > + unsigned int eats; > + unsigned int cfg; > + int ret; > + > + if (!(master->smmu->features & ARM_SMMU_FEAT_NESTING)) > + return ERR_PTR(-EOPNOTSUPP); > + > + /* > + * Must support some way to prevent the VM from bypassing the cache > + * because VFIO currently does not do any cache maintenance. > + */ > + if (!(fwspec->flags & IOMMU_FWSPEC_PCI_RC_CANWBS) && > + !(master->smmu->features & ARM_SMMU_FEAT_S2FWB)) > + return ERR_PTR(-EOPNOTSUPP); > + > + ret = iommu_copy_struct_from_user(&arg, user_data, > + IOMMU_HWPT_DATA_ARM_SMMUV3, ste); > + if (ret) > + return ERR_PTR(ret); > + > + if (flags || !(master->smmu->features & ARM_SMMU_FEAT_TRANS_S1)) > + return ERR_PTR(-EOPNOTSUPP); A bit redundant to the first sanity against ARM_SMMU_FEAT_NESTING, since ARM_SMMU_FEAT_NESTING includes ARM_SMMU_FEAT_TRANS_S1. > + > + if (!(parent->type & __IOMMU_DOMAIN_PAGING)) > + return ERR_PTR(-EINVAL); > + > + smmu_parent = to_smmu_domain(parent); > + if (smmu_parent->stage != ARM_SMMU_DOMAIN_S2 || Maybe "!smmu_parent->nest_parent" instead. [---] > + smmu_parent->smmu != master->smmu) > + return ERR_PTR(-EINVAL); It'd be slightly nicer if we do all the non-arg validations prior to calling iommu_copy_struct_from_user(). Then, the following arg validations would be closer to the copy(). > + > + /* EIO is reserved for invalid STE data. */ > + if ((arg.ste[0] & ~STRTAB_STE_0_NESTING_ALLOWED) || > + (arg.ste[1] & ~STRTAB_STE_1_NESTING_ALLOWED)) > + return ERR_PTR(-EIO); [---] > /* The following are exposed for testing purposes. */ > struct arm_smmu_entry_writer_ops; > struct arm_smmu_entry_writer { > @@ -830,6 +849,7 @@ struct arm_smmu_master_domain { > struct list_head devices_elm; > struct arm_smmu_master *master; > ioasid_t ssid; > + u8 nest_parent; Would it be nicer to match with the one in struct arm_smmu_domain: + bool nest_parent : 1; ? > + * struct iommu_hwpt_arm_smmuv3 - ARM SMMUv3 Context Descriptor Table info > + * (IOMMU_HWPT_DATA_ARM_SMMUV3) > + * > + * @ste: The first two double words of the user space Stream Table Entry for > + * a user stage-1 Context Descriptor Table. Must be little-endian. > + * Allowed fields: (Refer to "5.2 Stream Table Entry" in SMMUv3 HW Spec) > + * - word-0: V, Cfg, S1Fmt, S1ContextPtr, S1CDMax > + * - word-1: S1DSS, S1CIR, S1COR, S1CSH, S1STALLD It seems that word-1 is missing EATS. Thanks Nicolin