Re: [PATCH v2 2/8] iommu/arm-smmu-v3: Use S2FWB when available

Nicolin Chen
2024-08-27T19:49:39Z

Hi Jason,

On Tue, Aug 27, 2024 at 12:51:32PM -0300, Jason Gunthorpe wrote:
> diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
> index f5d9fd1f45bf49..9b3658aae21005 100644
> --- a/drivers/iommu/io-pgtable-arm.c
> +++ b/drivers/iommu/io-pgtable-arm.c
> @@ -106,6 +106,18 @@
> #define ARM_LPAE_PTE_HAP_FAULT (((arm_lpae_iopte)0) << 6)
> #define ARM_LPAE_PTE_HAP_READ (((arm_lpae_iopte)1) << 6)
> #define ARM_LPAE_PTE_HAP_WRITE (((arm_lpae_iopte)2) << 6)
> +/*
> + * For !FWB these code to:
> + * 1111 = Normal outer write back cachable / Inner Write Back Cachable
> + * Permit S1 to override
> + * 0101 = Normal Non-cachable / Inner Non-cachable
> + * 0001 = Device / Device-nGnRE
> + * For S2FWB these code:
> + * 0110 Force Normal Write Back
> + * 0101 Normal* is forced Normal-NC, Device unchanged
> + * 0001 Force Device-nGnRE
> + */
> +#define ARM_LPAE_PTE_MEMATTR_FWB_WB (((arm_lpae_iopte)0x6) << 2)

The other part looks good. Yet, would you mind sharing the location
that defines this 0x6 explicitly?

I am looking at DDI0487K, directed from 13.1.6 in SMMU RM and its
Reference:
[2] Arm Architecture Reference Manual for A-profile architecture.
(ARM DDI 0487) Arm Ltd.

Where it has the followings in D8.6.6:
"For stage 2 translations, if FEAT_MTE_PERM is not implemented, then
FEAT_S2FWB has all of the following effects on the MemAttr[3:2] bits:
- MemAttr[3] is RES0.
- The value of MemAttr[2] determines the interpretation of the
MemAttr[1:0] bits.
For stage 2 translations, if FEAT_MTE_PERM is implemented, then
MemAttr[3] is not RES0 and all bits of MemAttr[3:0] determine the
memory region type and Cacheability attributes.
For stage 2 translations, if FEAT_MTE_PERM is implemented, then all
of the following values of MemAttr[3:2] apply:
- 0b10 is Reserved.
- All other values determine the interpretation of the MemAttr[1:0]
bits.
For stage 2 translations, if MemAttr[2] is 0, or if FEAT_MTE_PERM is
implemented and MemAttr[3:2] is 0b00, then the MemAttr[1:0] bits
define Device memory attributes as shown in the following table:"

So, MemAttr[3:2] seems to be 00b or 10b depending on FEAT_MTE_PERM,
either of which would never result in 0x6?

Thanks
Nicolin